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DS90LV028A Datasheet(PDF) 1 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. DS90LV028A
Description  3V LVDS Dual CMOS Differential Line Receiver
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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DS90LV028A Datasheet(HTML) 1 Page - National Semiconductor (TI)

 
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DS90LV028A
3V LVDS Dual CMOS Differential Line Receiver
General Description
The DS90LV028A is a dual CMOS differential line receiver
designed for applications requiring ultra low power dissipa-
tion, low noise and high data rates. The device is designed to
support data rates in excess of 400 Mbps (200 MHz) utilizing
Low Voltage Differential Signaling (LVDS) technology.
The DS90LV028A accepts low voltage (350 mV typical) dif-
ferential input signals and translates them to 3V CMOS
output levels. The receiver also supports open, shorted and
terminated (100
Ω) input fail-safe. The receiver output will be
HIGH for all fail-safe conditions. The DS90LV028A has a
flow-through design for easy PCB layout.
The DS90LV028A and companion LVDS line driver provide a
new alternative to high power PECL/ECL devices for high
speed point-to-point interface applications.
Features
n >
400 Mbps (200 MHz) switching rates
n
50 ps differential skew (typical)
n
0.1 ns channel-to-channel skew (typical)
n
2.5 ns maximum propagation delay
n
3.3V power supply design
n
Flow-through pinout
n
Power down high impedance on LVDS inputs
n
Low Power design (18mW @ 3.3V static)
n
Interoperable with existing 5V LVDS networks
n
Accepts small swing (350 mV typical) differential signal
levels
n
Supports open, short and terminated input fail-safe
n
Conforms to ANSI/TIA/EIA-644 Standard
n
Industrial temperature operating range
(−40˚C to +85˚C)
n
Available in SOIC and space saving LLP package
Connection Diagrams
SOIC
10007701
Order Number DS90LV028ATM
See NS Package Number M08A
LLP (Top View)
10007725
Order Number DS90LV028ATLD
See NS Package Number LDC08A
Functional Diagram
10007702
Truth Table
INPUTS
OUTPUT
[R
IN+]−[RIN−]
R
OUT
V
ID
≥ 0.1V
H
V
ID
≤ −0.1V
L
Full Fail-safe
OPEN/SHORT
or Terminated
H
August 2005
© 2005 National Semiconductor Corporation
DS100077
www.national.com


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