Transmitter Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Min

Typ

Max

Units

LLHT

LVDS Low-to-High Transition Time, (Figure 2),

PRE = 0.75V (disabled)

0.14

0.7

ns

LVDS Low-to-High Transition Time, (Figure 2),

PRE = Vcc (max)

0.11

0.6

ns

LHLT

LVDS High-to-Low Transition Time, (Figure 2),

PRE = 0.75V (disabled)

0.16

0.8

ns

LVDS High-to-Low Transition Time, (Figure 2),

PRE = Vcc (max)

0.11

0.7

ns

TBIT

Transmitter Bit Width

f = 66 MHz,

112MHz

1/7 TCIP

ns

TPPOS

Transmitter Pulse Positions -

Normalized

f=65to112

MHz

− 200

0

+200

ps

TJCC

Tranmitter Jitter - Cycle-to-Cycle

100

ps

TCCS

TxOUT Channel to Channel Skew

40

ps

TSTC

TxIN Setup to TxCLK IN, (Figure 5)

2.5

ns

THTC

TxIN Hold to TxCLK IN, (Figure 5)0

ns

TPDL

Transmitter Propagation Delay - Latency, (Figure 7)

1.5(TCIP)+3.72

1.5(TCIP)+4.4

1.5(TCIP)+6.24

ns

TPLLS

Transmitter Phase Lock Loop Set, (Figure 9)10

ms

TPDD

Transmitter Powerdown Delay, (Figure 11)

100

ns

Receiver Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Min

Typ

Max

Units

CLHT

CMOS/TTL Low-to-High Transition Time, Rx data out,

(Figure 3)

2.0

ns

CMOS/TTL Low-to-High Transition Time, Rx clock

out, (Figure 3)

1.0

ns

CHLT

CMOS/TTL High-to-Low Transition Time, Rx data out,

(Figure 3)

2.0

ns

CMOS/TTL High-to-Low Transition Time, Rx clock

out, (Figure 3)

1.0

ns

RCOP

RxCLK OUT Period, (Figure 6)

8.928

T

15.38

ns

RCOH

RxCLK OUT High Time, (Figure 6),

(Note 4)

f = 112 MHz

3.5

ns

f = 66 MHz

6.0

ns

RCOL

RxCLK OUT Low Time, (Figure 6),

(Note 4)

f = 112 MHz

3.5

ns

f = 66 MHz

6.0

ns

RSRC

RxOUT Setup to RxCLK

OUT,(Figure 6)

f = 112 MHz

2.4

ns

f = 66 MHz

3.6

ns

RHRC

RxOUT Hold to RxCLK OUT,

(Figure 6), (Note 4)

f = 112 MHz

3.4

ns

f = 66 MHz

6.0

ns

RPDL

Receiver Propagation Delay - Latency, (Figure 8)

3(TCIP)+4.0

3(TCIP)+4.8

3(TCIP)+6.5

ns

RPLLS

Receiver Phase Lock Loop Set, (Figure 10)10

ms

RPDD

Receiver Powerdown Delay, (Figure 12)1

µs

www.national.com

5