DS90CR218A datasheet(10/11 Pages) NSC

Part #	DS90CR218A

Description	3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 12 MHz to 85 MHz

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Manufacturer	NSC [National Semiconductor (TI)]

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Applications Information (Continued)

DECOUPLING CAPACITORS

Bypassing capacitors are needed to reduce the impact of

switching noise which could limit performance. For a conser-

vative approach three parallel-connected decoupling capaci-

tors (Multi-Layered Ceramic type in surface mount form fac-

tor) between each V

CC

and the ground plane(s) are

recommended. The three capacitor values are 0.1 µF, 0.01

µF and 0.001 µF. An example is shown in Figure 11. The

designer should employ wide traces for power and ground

and ensure each capacitor has its own via to the ground

plane. If board space is limiting the number of bypass ca-

pacitors, the PLL V

CC should receive the most filtering/

bypassing. Next would be the LVDS V

CC pins and finally the

logic V

CC pins.

CLOCK JITTER

The CHANNEL LINK devices employ a PLL to generate and

recover the clock transmitted across the LVDS interface. The

width of each bit in the serialized LVDS data stream is

one-seventh the clock period. For example, a 85 MHz clock

has a period of 11.76 ns which results in a data bit width of

1.68 ns. Differential skew (

∆t within one differential pair),

interconnect skew (

∆t of one differential pair to another) and

clock jitter will all reduce the available window for sampling

the LVDS serial data streams. Care must be taken to ensure

that the clock input to the transmitter be a clean low noise

signal. Individual bypassing of each V

CC to ground will mini-

mize the noise passed on to the PLL, thus creating a low

jitter LVDS clock. These measures provide more margin for

channel-to-channel skew and interconnect skew as a part of

the overall jitter/skew budget.

COMMON-MODE vs. DIFFERENTIAL MODE NOISE

MARGIN

The typical signal swing for LVDS is 300 mV centered at

+1.2V. The CHANNEL LINK receiver supports a 100 mV

threshold therefore providing approximately 200 mV of dif-

ferential noise margin. Common-mode protection is of more

importance to the system’s operation due to the differential

data transmission. LVDS supports an input voltage range of

Ground to +2.4V. This allows for a ±1.0V shifting of the

center point due to ground potential differences and

common-mode noise.

10108025

FIGURE 11. CHANNEL LINK

Decoupling Configuration

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Texas Instruments	DS90CR218AMTDX/NOPB	911Kb / 17P	[Old version datasheet] 3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 12 MHz to 85 MHz

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Manufacturer	Part #	Datasheet	Description
Texas Instruments	DS90CR218A	911Kb / 17P	[Old version datasheet] 3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 12 MHz to 85 MHz
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