 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ISL9208IRZ Datasheet(PDF) 8 Page - Intersil Corporation |
|
||||||||||||||||||||||||||||||
ISL9208IRZ Datasheet(HTML) 8 Page - Intersil Corporation |
|
|
8 / 28 page  8 FN6446.1 November 2, 2007 SERIAL INTERFACE CHARACTERISTICS SCL Clock Frequency fSCL 100 kHz Pulse Width Suppression Time at SDA and SCL Inputs tIN Any pulse narrower than the max spec is suppressed. 50 ns SCL Falling Edge to SDA Output Data Valid tAA From SCL falling crossing VIH(min), until SDA exits the VIL(max) to VIH(min) window. 3.5 µs Time the Bus Must Be Free Before Start of New Transmission tBUF SDA crossing VIH(min) during a STOP condition to SDA crossing VIH(min) during the following START condition. 4.7 µs Clock Low Time tLOW Measured at the VIL(max) crossing. 4.7 µs Clock High Time tHIGH Measured at the VIH(min) crossing. 4.0 µs Start Condition Setup Time tSU:STA SCL rising edge to SDA falling edge. Both crossing the VIH(min) level. 4.7 µs Start Condition Hold Time tHD:STA From SDA falling edge crossing VIL(max) to SCL falling edge crossing VIH(min). 4.0 µs Input Data Setup Time tSU:DAT From SDA exiting the VIL(max) to VIH(min) window to SCL rising edge crossing VIL(min). 250 ns Input Data Hold Time tHD:DAT From SCL falling edge crossing VIH(min) to SDA entering the VIL(max) to VIH(min) window. 300 µs Stop Condition Setup Time tSU:STO From SCL rising edge crossing VIH(min) to SDA rising edge crossing VIL(max). 4.0 µs Stop Condition Hold Time tHD:STO From SDA rising edge to SCL falling edge. Both crossing VIH(min). 4.0 µs Data Output Hold Time tDH From SCL falling edge crossing VIL(max) until SDA enters the VIL(max) to VIH(min) window. (Note 4) 0ns SDA and SCL Rise Time tR From VIL(max) to VIH(min). 1000 ns SDA and SCL Fall Time tF From VIH(min) to VIL(max). 300 ns Capacitive Loading Of SDA Or SCL Cb Total on-chip and off-chip 400 pF SDA and SCL Bus Pull-up Resistor- Off Chip ROUT Maximum is determined by tR and tF. For CB = 400pF, max is about 2kΩ ~ 2.5kΩ For CB = 40pF, max is about 15kΩ to 20kΩ 1k Ω Input Leakage Current (SCL, SDA) ILI -10 10 µA Input Buffer Low Voltage (SCL, SDA) VIL Voltage relative to VSS of the device. -0.3 VRGO x 0.3 V Input Buffer High Voltage (SCL, SDA) VIH Voltage relative to VSS of the device. VRGO x 0.7 VRGO +0.1 V V Output Buffer Low Voltage (SDA) VOL IOL = 1mA 0.4 V SDA and SCL Input Buffer Hysteresis I2CHYST Sleep bit = 0 0.05 * VRGO V NOTES: 3. Power up of the device requires all VCELL1, VCELL2, VCELL3, and VCC to be above the limits specified. 4. The device provides an internal hold time of at least 300ns for the SDA signal to bridge the unidentified region of the falling edge of SCL. 5. Typical +125°C ±10%, based on design and characterization data. 6. Typical 5 Ω ±2Ω, based on design and characterization data. 7. Maximum output capacitance = 15pF. Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued) PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT ISL9208 |
Similar Part No. - ISL9208IRZ |
|
Similar Description - ISL9208IRZ |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
