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CLC030VEC Datasheet(PDF) 10 Page - National Semiconductor (TI) |
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CLC030VEC Datasheet(HTML) 10 Page - National Semiconductor (TI) |
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10 / 29 page  Device Operation (Continued) The ACLK input controls data flow through the port. The operation and frequency of ACLK is independent of the video data clock, VCLK. However, the frequency of ACLK must be less than or equal to VCLK. There is no low fre- quency limit for ACLK when it is being used for control register access. When theANC/CTRL input is a logic-high, ACLK affects only the ancillary data FIFO operation. When the ANC/CTRL input is a logic-low, ACLK affects only the control register operation. Inputs AD[9:0], RD/WR and ANC/CTRL have internal pull down devices. ACLK does not have an internal pull down device. CONTROL DATA READ FUNCTIONS Control data is written to and read from the CLC030 using the lower-order 8 bits AD[7:0] of the Ancillary/Control Data Port. This control data initializes, monitors and controls op- eration of the CLC030. The upper two bits AD[9:8] of the port are handshaking signals with the device accessing the port. AD[9:8] must be driven as 00b (0XXh, where XX are AD[7:0]) when either a control register read or write address is being written to the port. AD[9:8] must be driven as 11b (3XXh, where XX are AD[7:0]) when control data is being written to the port. When control data is being read from the port, the CLC030 will output AD[9:8] as 10b (2XXh, where XX are output data AD[7:0]) and may be ignored by the monitoring system. Note: When power is first applied to the device or after it is reset, the Ancillary and Control Data Port must be initial- ized to receive data. This is done by toggling ACLK three (3) times. Figure 1 shows the sequence of clock and control signals for reading control data from the ancillary/control data port. The Control Data Read mode is entered by making the ANC/CTRL input low and the RD/WR input high. Next, the 8-bit address of the control register set to be accessed is placed on port bits AD[7:0]. When a control register read address is being written to the port, AD[9:8] must be driven as 00b (0XXh, where XX are AD[7:0]). ACLK is then toggled. The address is captured on the rising edge of ACLK. Ob- serve the port input hold timing specification. Data from the selected register is driven by the port within a few nanoseconds immediately following the rising edge of ACLK. To avoid contention with the port, the address driver should be turned off or tri-stated immediately after the ad- dress is clocked into the device. Data may be read by external devices at any time after the removal of the address signal. Output data will be driven until the next rising edge of ACLK. When the host system finishes reading the data, toggle ACLK again. This second clock resets the port from drive to receive mode and readies the port for another access cycle. When control data is being read from the port, the CLC030 will output AD[9:8] as 10b (2XXh, where XX are output data AD[7:0]) and may be ignored by the monitoring system. Example: Read the Full-field Flags via the AD port. 1. Set ANC/CTRL to a logic-low. 2. Set RD/WR to a logic-high. 3. Present 001h to AD[9:0] as the register address. 4. Toggle ACLK. 5. Release the bus driving the AD port. 6. Read the data present on the AD port. The Full-field Flags are bits AD[4:0]. 7. Toggle ACLK to release the AD port. 20000309 FIGURE 1. Control Data Read Timing (2 read and 1 write cycle shown) www.national.com 10 |
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