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CY28437ZXCT Datasheet(PDF) 3 Page - SpectraLinear Inc

Part # CY28437ZXCT
Description  Clock Generator for Intel Grantsdale Chipset
Download  22 Pages
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Manufacturer  SPECTRALINEAR [SpectraLinear Inc]
Direct Link  http://www.spectralinear.com
Logo SPECTRALINEAR - SpectraLinear Inc

CY28437ZXCT Datasheet(HTML) 3 Page - SpectraLinear Inc

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CY28437
Rev 1.0, November 20, 2006
Page 3 of 22
Frequency Select Pins (FS_[A:E])
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A, FS_B, FS_C, FS_D, and
FS_E inputs prior to VTT_PWRGD# assertion (as seen by the
clock synthesizer). Upon VTT_PWRGD# being sampled LOW
by the clock chip (indicating processor VTT voltage is stable),
the clock chip samples the FS_A, FS_B, FS_C, FS_D, and
FS_E input values. For all logic levels of FS_A, FS_B, FS_C,
FS_D, and FS_E, VTT_PWRGD# employs a one-shot
functionality in that once a valid LOW on VTT_PWRGD# has
been sampled, all further VTT_PWRGD#, FS_A, FS_B, FS_C,
FS_D, and FS_E transitions will be ignored, except in test
mode.
FS_C is a three-level input, when sampled at a voltage greater
than 2.1V by VTTPWRGD#, the device will enter test mode as
selected by the voltage level on the FS_B input.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Figure 1. CPU and SRC Frequency Select Tables
FS_D
FS_C
FS_B
FS_A
CPU
SRC
CPUPLL
Gear
Constants
CPUM
divider
CPUN
DEFAULT
CPUN
allowable
rangefor
DAF
SRCPLL
Gear
Constants
SRCM
divider (not
changeable
byuser)
SRCN
DEFAULT
SRCN
allowable
rangefor
DAF
FSEL_3
FSEL_2
FSEL_1
FSEL_0
(MHz)
(MHz)
(G)
0
1
0
1
100
100
30
60
200
200- 250
30
60
200 200- 266
0
0
0
1
133.3333333
100
40
60
200
200- 250
30
60
200 200- 266
0
0
1
1
166.6666667
100
60
63
175
175- 262
30
60
200 200- 266
0
0
1
0
200
100
60
60
200
200- 250
30
60
200 200- 266
0
0
0
0
266.6666667
100
80
60
200
200- 250
30
60
200 200- 266
0
1
0
0
333.3333333
100
120
63
175
175- 262
30
60
200 200- 266
0
1
1
0
400
100
120
60
200
200- 250
30
60
200 200- 266
1
1
0
1
100.952381
100
30
63
212
212- 262
30
60
200 200- 266
1
0
0
1
133.968254
100
40
63
211
211- 262
30
60
200 200- 266
1
0
1
1
167
100
60
60
167
167- 250
30
60
200 200- 266
1
0
1
0
200.952381
100
60
63
211
211- 262
30
60
200 200- 266
1
0
0
0
266.6666667
100
80
60
200
200- 250
30
60
200 200- 266
1
1
0
0
334
100
120
60
167
167- 250
30
60
200 167- 266
1
1
1
0
400.6451613
100
120
62
207
207- 258
30
60
200 167- 266
X
HIGH
LOW
X
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
X
HIGH
HIGH
X
REF/N
REF/N
REF/N
REF/N
REF/N
REF/N
Input Conditions
Output Frequency


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