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CY28412OC Datasheet(PDF) 4 Page - SpectraLinear Inc

Part # CY28412OC
Description  Clock Generator for Intel짰 Grantsdale Chipset
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Manufacturer  SPECTRALINEAR [SpectraLinear Inc]
Direct Link  http://www.spectralinear.com
Logo SPECTRALINEAR - SpectraLinear Inc

CY28412OC Datasheet(HTML) 4 Page - SpectraLinear Inc

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CY28412
Rev 1.0, November 20, 2006
Page 4 of 16
Control Registers
....
......................
39:46
Data byte from slave – 8 bits
....
Data Byte (N – 1) – 8 bits
47
Acknowledge from master
....
Acknowledge from slave
48:55
Data byte from slave – 8 bits
....
Data Byte N – 8 bits
56
Acknowledge from master
....
Acknowledge from slave
....
Data byte N from slave – 8 bits
....
Stop
....
Acknowledge from master
....
Stop
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Byte Read Protocol
Bit
Description
Bit
Description
1Start
1Start
2:8
Slave address – 7 bits
2:8
Slave address – 7 bits
9Write = 0
9
Write = 0
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code – 8 bits
'100xxxxx' stands for byte operation, bits[6:0] of the
command code represents the offset of the byte to
be accessed
11:18
Command Code – 8 bits
'100xxxxx' stands for byte operation, bits[6:0] of
the command code represents the offset of the
byte to be accessed
19
Acknowledge from slave
19
Acknowledge from slave
20:27
Data byte from master – 8 bits
20
Repeat start
28
Acknowledge from slave
21:27
Slave address – 7 bits
29
Stop
28
Read = 1
29
Acknowledge from slave
30:37
Data byte from slave – 8 bits
38
Acknowledge from master
39
Stop
Table 3. Block Read and Block Write Protocol (continued)
Block Write Protocol
Block Read Protocol
Bit
Description
Bit
Description
Byte 0:Control Register 0
Bit
@Pup
Name
Description
7
1
CPUT2_ITP/SRCT6
CPUC2_ITP/SRCC6
CPU[T/C]2_ITP/SRC[T/C]6 Output Enable
0 = Disable (Hi-Z), 1 = Enable
6
1
SRC[T/C]5
SRC[T/C]5 Output Enable
0 = Disable (Hi-Z), 1 = Enable
5
1
SRC[T/C]4
SRC[T/C]4 Output Enable
0 = Disable (Hi-Z), 1 = Enable
4
1
SRC[T/C]3
SRC[T/C]3 Output Enable
0 = Disable (Hi-Z), 1 = Enable
3
1
SATAT/C]
SATA[T/C] Output Enable
0 = Disable (Hi-Z), 1 = Enable
2
1
SRC[T/C]2
SRC[T/C]2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
1
1
SRC[T/C]1
SRC[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
0
1
SRC[T/C]0
SRC[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable


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