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CY28412OC Datasheet(PDF) 2 Page - SpectraLinear Inc |
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CY28412OC Datasheet(HTML) 2 Page - SpectraLinear Inc |
2 / 16 page CY28412 Rev 1.0, November 20, 2006 Page 2 of 16 Pin Definitions Pin No. Name Type Description 47,46,44,43 CPUT/C O, DIF Differential CPU clock outputs. 39,38 CPUT2_ITP/SRCT6, CPUC2_ITP/SRCC6 O, DIF Selectable Differential CPU or SRC clock output. ITP_EN = 0 @ VTT_PWRGD# assertion = SRC6 ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2 16,17 DOT96T, DOT96C O, DIF Fixed 96-MHz clock output. 55, 54 REF0/FS_C, REF1/FS_A I/O 14.318-MHz reference clock/3.3V-tolerant input for CPU frequency selection. Input is latched upon assertion (LOW) of VTT_PWRGD#/PD Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. 14 USB48/FS_B I/O Fixed 48-MHz USB clock output/3.3V-tolerant input for CPU frequency selection. Input is latched upon assertion (LOW) of VTT_PWRGD#/PD Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. 42 IREF I A precision resistor is attached to this pin, which is connected to the internal current reference. 1,2,5,6,7,8 PCI[0:5] O, SE 33-MHz clocks. 11 TEST_SEL/PCIF0 I/O Free-running 33-MHz clocks/ 3.3V-tolerant input for selecting test mode. Input is latched upon assertion (LOW) of VTT_PWRGD#/PD 1 = All outputs are three-stated for test 0 = All outputs normal operation **This input has an internal pull-down resistor. 12 ITP_EN/PCIF1 I/O, SE Free-running 33-MHz clock/CPU2 select (sampled on the VTT_PWRGD# assertion). 1 = CPU2_ITP, 0 = SRC6 49 SCLK I SMBus-compatible SCLOCK. 50 SDATA I/O SMBus-compatible SDATA. 27,28 SATAT, SATAC O, DIF Differential serial reference clock. Recommended output for SATA. 19,20,21,22, 25,26,30,31, 32,33,35,36 SRCT/C[0:5] O, DIF Differential serial reference clocks. 13 VDD_48 PWR 3.3V power supply for outputs. 45 VDD_CPU PWR 3.3V power supply for outputs. 3,10 VDD_PCI PWR 3.3V power supply for outputs. 56 VDD_REF PWR 3.3V power supply for outputs. 23,29,37 VDD_SRC PWR 3.3V power supply for outputs. 40 VDD_A PWR 3.3V power supply for PLL. 15 GND_48 GND Ground for outputs. 48 GND_CPU GND Ground for outputs. 4,9 GND_PCI GND Ground for outputs. 53 GND_REF GND Ground for outputs. 24,34 GND_SRC GND Ground for outputs. 41 GND_A GND Ground for PLL. 18 VTT_PWRGD#/PD I, PU 3.3V LVTTL input is a level sensitive strobe used to latch the REF0/FSC, REF1/FSA, USB48/FSB, TEST_SEL/PCIF0 and ITP_EN/PCIF1 inputs. After VTT_PWRGD# (active LOW) assertion, this pin becomes a realtime input for asserting power-down (active HIGH). 52 X1 I 14.318-MHz crystal input. 51 X2 O, SE 14.318-MHz crystal output. |
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