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CY28412 Datasheet(PDF) 6 Page - SpectraLinear Inc

Part # CY28412
Description  Clock Generator for Intel짰 Grantsdale Chipset
Download  16 Pages
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Manufacturer  SPECTRALINEAR [SpectraLinear Inc]
Direct Link  http://www.spectralinear.com
Logo SPECTRALINEAR - SpectraLinear Inc

CY28412 Datasheet(HTML) 6 Page - SpectraLinear Inc

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CY28412
Rev 1.0, November 20, 2006
Page 6 of 16
2
0
SRC2
Allow control of SRC[T/C]2 with assertion of SW PCI_STP#
0 = Free-running, 1 = Stopped with SW PCI_STP#
1
0
SRC1
Allow control of SRC[T/C]1 with assertion of SW PCI_STP#
0 = Free-running, 1 = Stopped with SW PCI_STP#
0
0
SRC0
Allow control of SRC[T/C]0 with assertion of SW PCI_STP#
0 = Free-running, 1 = Stopped with SW PCI_STP#
Byte 4: Control Register 4
Bit
@Pup
Name
Description
7
0
RESERVED
RESERVED, Set = 0
6
0
DOT96[T/C]
DOT_PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Hi-Z
5
0
PCIF1
Allow control of PCIF2 with assertion of SW PCI_STP#
0 = Free-running, 1 = Stopped with SW PCI_STP#
4
0
PCIF0
Allow control of PCIF1 with assertion of SW PCI_STP#
0 = Free-running, 1 = Stopped with SW PCI_STP#
3
0
RESERVED
RESERVED, Set = 0
2
1
RESERVED
RESERVED, Set = 1
1
1
RESERVED
RESERVED, Set = 1
0
1
RESERVED
RESERVED, Set = 1
Byte 5: Control Register 5
Bit
@Pup
Name
Description
7
0
SRC[T/C][6:0],SATA[T/C] SRC[T/C], SATA[T/C]Stop Drive Mode
0 = Driven when SW PCI_STP# asserted,1 = Hi-Z when PCI_STP#
asserted
6
0
RESERVED
RESERVED, Set = 0
5
0
RESERVED
RESERVED, Set = 0
4
0
RESERVED
RESERVED, Set = 0
3
0
SRC[T/C][6:0],SATA[T/C] SRC[T/C], SATA[T/C] PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
2
0
CPU[T/C]2
CPU[T/C]2 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
1
0
CPU[T/C]1
CPU[T/C]1 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
0
0
CPU[T/C]0
CPU[T/C]0 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
Byte 3: Control Register 3 (continued)
Bit
@Pup
Name
Description


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