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CY28411 Datasheet(PDF) 11 Page - SpectraLinear Inc |
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CY28411 Datasheet(HTML) 11 Page - SpectraLinear Inc |
11 / 18 page CY28411 Rev 1.0, November 22, 2006 Page 11 of 18 PCI_STP# Assertion[1] The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function. The set-up time for capturing PCI_STP# going LOW is 10 ns (tSU). (See Figure 9.) The PCIF clocks will not be affected by this pin if their corresponding control bit in the SMBus register is set to allow them to be free running. PCI_STP# Deassertion The deassertion of the PCI_STP# signal will cause all PCI and stoppable PCIF clocks to resume running in a synchronous manner within two PCI clock periods after PCI_STP# transi- tions to a high level. Note: 1. The PCI STOP function is controlled by two inputs. One is the device PCI_STP# pin number 34 and the other is SMBus byte 0 bit 3. These two inputs are logically OR’ed. If either the external pin or the internal SMBus register bit is set low then the stoppable PCI clocks will be stopped in a logic low state. Reading SMBus Byte 0 Bit 3 will return a 0 value if either of these control bits are set LOW thereby indicating the device’s stoppable PCI clocks are not running. DOT96C DOT96T CPUC(Stoppable) CPUT(Stoppable) CPUC(Free Running) CPUT(Free Running) PD 1.8mS CPU_STOP# Figure 8. CPU_STP# = Hi-Z, CPU_PD = Hi-Z, DOT_PD = tHi-Z Tsu PCI_STP# PCI_F PCI SRC 100MHz Figure 9. PCI_STP# Assertion Waveform PCI_STP# PCI_F PCI SRC 100MHz Tsu Tdrive_SRC Figure 10. PCI_STP# Deassertion Waveform |
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