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CY28409OC Datasheet(PDF) 9 Page - SpectraLinear Inc |
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CY28409OC Datasheet(HTML) 9 Page - SpectraLinear Inc |
9 / 16 page CY28409 Rev 1.0, November 22, 2006 Page 9 of 16 PD# Deassertion The power-up latency between PD# rising to a valid logic ‘1’ level and the starting of all clocks is less than 1.8 ms. CPU_STP# Assertion The CPU_STP# signal is an active LOW input used for synchronous stopping and starting the CPU output clocks while the rest of the clock generator continues to function. When the CPU_STP# pin is asserted, all CPU outputs that are set with the SMBus configuration to be stoppable via assertion of CPU_STP# will be stopped after being sampled by two rising edges of the internal CPUT clock. The final states of the stopped CPU signals are CPUT = HIGH and CPUC = LOW. There is no change to the output drive current values during the stopped state. The CPUT is driven HIGH with a current value equal to (Mult 0 ‘select’) x (Iref), and the CPUC signal will not be driven. Due to the external pull-down circuitry, CPUC will be LOW during this stopped state. CPU_STP# Deassertion The deassertion of the CPU_STP# signal will cause all CPU outputs that were stopped to resume normal operation in a synchronous manner. Synchronous manner meaning that no short or stretched clock pulses will be produce when the clock resumes. The maximum latency from the deassertion to active outputs is no more than two CPU clock cycles. REF Tdrive_PWRDN# <300 s, >200 mV PD# CPUC, 133MHz CPUT, 133MHz SRCC 100MHz 3V66, 66MHz USB, 48MHz PCI, 33MHz SRCT 100MHz Tstable <1.8 ms Figure 4. Power-down Deassertion Timing Waveform CPU_STP# CPUT CPUC Figure 5. CPU_STP# Assertion Waveform CPU_STP# CPUT CPUC CPU Internal Tdrive_CPU_STP#, 10 ns > 200 mV Figure 6. CPU_STP# Deassertion Waveform |
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