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CY28400-2 Datasheet(PDF) 1 Page - SpectraLinear Inc |
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CY28400-2 Datasheet(HTML) 1 Page - SpectraLinear Inc |
1 / 15 page 100 MHz Differential Buffer for PCI Express and SATA CY28400-2 Rev 1.0, November 21, 2006 Page 1 of 15 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 www.SpectraLinear.com Features • CK409 and CK410 companion buffer • Four differential 0.7V clock output pairs • OE_INV input for inverting OE, PWRDWN, and SRC_STP active levels • Individual OE controls • Low CTC jitter (< 50 ps) • Programmable bandwidth • SRC_STP power management control • SMBus Block/Byte/Word Read and Write support • 3.3V operation • PLL Bypass-configurable • Divide by 2 programmable outputs • 28-pin SSOP and TSSOP packages Functional Description The CY28400-2 is a differential buffer and serves as a companion device to the CK409 or CK410 clock generator. The device is capable of distributing the Serial Reference Clock (SRC) in PCI Express and SATA implementations. Block Diagram Pin Configuration PLL/BYPASS# DIFT2 DIFC2 DIFT1 DIFC1 DIFT5 DIFC5 DIFT6 DIFC6 Output Buffer Output Control PLL DIV SMBus Controller SRC_STP PWRDWN SCLK SDATA SRCT_IN SRCC_IN HIGH_BW# OE_1, OE_6 OE_INV 28 SSOP/TSSOP VDD SRCT_IN VSS VDD DIFT1 DIFC1 OE_1 DIFT2 DIFC2 VDD PLL/BYPASS# SCLK SDATA VDD_A VSS_A SRC_STP PWRDWN HIGH_BW# DIFC5 VDD DIFT5 DIFC6 0E_6 DIFT6 OE_INV VDD IREF 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SRCC_IN |
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