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DS90CF363B Datasheet(PDF) 4 Page - National Semiconductor (TI) |
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DS90CF363B Datasheet(HTML) 4 Page - National Semiconductor (TI) |
4 / 11 page Transmitter Switching Characteristics (Continued) Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Min Typ Max Units TPPos0 Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note 5) f = 25MHz −0.45 0 +0.45 ns TPPos1 Transmitter Output Pulse Position for Bit 1 5.26 5.71 6.16 ns TPPos2 Transmitter Output Pulse Position for Bit 2 10.98 11.43 11.88 ns TPPos3 Transmitter Output Pulse Position for Bit 3 16.69 17.14 17.59 ns TPPos4 Transmitter Output Pulse Position for Bit 4 22.41 22.86 23.31 ns TPPos5 Transmitter Output Pulse Position for Bit 5 28.12 28.57 29.02 ns TPPos6 Transmitter Output Pulse Position for Bit 6 33.84 34.29 34.74 ns TSTC TxIN Setup to TxCLK IN (Figure 6 ) 2.5 ns THTC TxIN Hold to TxCLK IN (Figure 6 ) 0.5 ns TCCD TxCLK IN to TxCLK OUT Delay (Figure 7 ) 50% duty cycle input clock is assumed, T A= −10˚C, and 65MHz for " Min ", T A = 70˚C, and 25MHz for " Max ", V CC = 3.6V 3.011 6.082 ns SSCG Spread Spectrum Clock support; Modulation frequency with a linear profile (Note 6) f=25 MHz 100KHz ± 2.5%/−5% f=40 MHz 100KHz ± 2.5%/−5% f=65 MHz 100KHz ± 2.5%/−5% TPLLS Transmitter Phase Lock Loop Set (Figure 8 ) 10 ms TPDD Transmitter Power Down Delay (Figure 10 ) 100 ns Note 5: The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temperature ranges. This parameter is functionality tested only on Automatic Test Equipment (ATE). Note 6: Care must be taken to ensure TSTC and THTC are met so input data are sampling correctly. This SSCG parameter only shows the performance of tracking Spread Spectrum Clock applied to TxCLK IN pin, and reflects the result on TxCLKOUT+ and TxCLK− pins. AC Timing Diagrams 20098704 FIGURE 1. “Worst Case” Test Pattern www.national.com 4 |
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