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DS90C387A Datasheet(PDF) 5 Page - National Semiconductor (TI) |
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DS90C387A Datasheet(HTML) 5 Page - National Semiconductor (TI) |
5 / 19 page Recommended Transmitter Input Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Min Typ Max Units TCIT TxCLK IN Transition Time (Figure 5) DUAL=Gnd or Vcc 1.0 2.0 3.0 ns DUAL=1/2Vcc 1.0 1.5 1.7 ns TCIP TxCLK IN Period (Figure 6) DUAL=Gnd or Vcc 8.928 T 30.77 ns DUAL=1/2Vcc 5.88 15.38 ns TCIH TxCLK in High Time (Figure 6) 0.35T 0.5T 0.65T ns TCIL TxCLK in Low Time (Figure 6) 0.35T 0.5T 0.65T ns TXIT TxIN Transition Time 1.5 6.0 ns Transmitter Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Min Typ Max Units LLHT LVDS Low-to-High Transition Time (Figure 3), PRE = 0.75V (disabled) 0.14 0.7 ns LVDS Low-to-High Transition Time (Figure 3), PRE = Vcc (max) 0.11 0.6 ns LHLT LVDS High-to-Low Transition Time (Figure 3), PRE = 0.75V (disabled) 0.16 0.8 ns LVDS High-to-Low Transition Time (Figure 3), PRE = Vcc (max) 0.11 0.7 ns TBIT Transmitter Output Bit Width DUAL=Gnd or Vcc 1/7 TCIP ns DUAL=1/2Vcc 2/7 TCIP ns TPPOS Transmitter Pulse Positions - Normalized f = 33 to 70 MHz −250 0 +250 ps f = 70 to 112 MHz −200 0 +200 ps TCCS TxOUT Channel to Channel Skew 100 ps TSTC TxIN Setup to TxCLK IN (Figure 6) 2.7 ns THTC TxIN Hold to TxCLK IN (Figure 6)0 ns TJCC Transmitter Jitter Cycle-to-cycle (Figures 13, 14) (Note 5), DUAL=Vcc f = 112 MHz 85 100 ps f = 85 MHz 60 75 ps f = 65 MHz 70 80 ps f = 56 MHz 100 120 ps f = 32.5 MHz 75 110 ps TPLLS Transmitter Phase Lock Loop Set (Figure 8)10 ms TPDD Transmitter Powerdown Delay (Figure 10) 100 ns www.national.com 5 |
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