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CY28347 Datasheet(PDF) 5 Page - SpectraLinear Inc |
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CY28347 Datasheet(HTML) 5 Page - SpectraLinear Inc |
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5 / 21 page  CY28347 Rev 1.0, November 20, 2006 Page 5 of 21 10 Acknowledge from slave 10 Acknowledge from slave 11:18 Command Code - 8 bits “1xxxxxxx” stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed 11:18 Command Code - 8 bits “1xxxxxxx” stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed 19 Acknowledge from slave 19 Acknowledge from slave 20:27 Data Byte from Master – 8 Bits 20 Repeat start 28 Acknowledge from slave 21:27 Slave address - 7 bits 29 Stop 28 Read 29 Acknowledge from slave 30:37 Data byte from slave - 8 bits 38 Not Acknowledge 39 Stop Table 6. Byte Read and Byte Write Protocol (continued) Byte 0: Frequency Select Register Bit @Pup Pin# Name Description 7 0 Reserved. 6 H/W Setting 21 FS2 For Selecting Frequencies see Table 1. 5 H/W Setting 10 FS1 For Selecting Frequencies see Table 1. 4 H/W Setting 1 FS0 For Selecting Frequencies see Table 1. 3 0 If this bit is programmed to “1,” it enables WRITES to bits (6:4,1) for selecting the frequency via software (SMBus) If this bit is programmed to a “0” it enables only READS of bits (6:4,1), which reflect the hardware setting of FS(0:3). 2 H/W Setting 11 Reserved Reserved 1 H/W Setting 20 FS3 For Selecting frequencies in Table 1. 0 H/W Setting 7 SELP4_K7# Only for reading the hardware setting of the CPU interface mode, status of SELP4_K7# strapping. Byte 1: CPU Clocks Register Bit @Pup Pin# Name Description 7 0 SSMODE 0 = Down Spread. 1 = Center Spread. See Table 10. 6 1 SSCG 1 = Enable (default). 0 = Disable 5 1 SST1 Select spread bandwidth. See Table 10. 4 1 SST0 Select spread bandwidth. See Table 10. 3 1 48,49 CPUCS_T/C_ EN# 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. 2 1 53,52 CPUOD_T/C_EN# 1 = output enabled (running). 0 = output disable asynchronously in a LOW state. 1 0 53,52 CPUT/C_PD_CNTRL In K7 mode, this bit is ignored. In P4 mode, when PD# asserted LOW, 0 = drive CPUT to 2xIref and CPUC LOW and 1 = three-state CPUT and CPUC. 0 1 11 MULT0 Only For reading the hardware setting of the Pin11 MULT0 value. Byte 2: PCI Clock Register Bit @Pup Pin# Name Description 7 0 PCI_DRV PCI clock output drive strength 0 = Normal, 1 = increase the drive strength 20%. 6 1 10 PCI_F 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. 5 1 Reserved, set = 1. |
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