CY28342OC datasheet(3/21 Pages) SPECTRALINEAR

Part #	CY28342OC

Description	High-performance SiS645/650 Pentium짰 4-Clock Synthesizer

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Manufacturer	SPECTRALINEAR [SpectraLinear Inc]

Direct Link	http://www.spectralinear.com

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CY28342

Rev 1.0, November 20, 2006

Page 3 of 21

Pin Description [2]

Name

PWR

I/O

Description

6XIN

I

Oscillator buffer input. Connect to a crystal or to an external clock.

7

XOUT

VDDR

O

Oscillator buffer output. Connect to a crystal. Do not connect when

an external clock is applied at XIN.

39,40,43,44

CPU (0:1)T,

CPU (0:1)C

VDDC

O

Differential host output clock pairs. See Table 1 for frequencies and

functionality.

16,17,20,23

PCI (0:5)

VDDP

O

PCI clock outputs. See Table 1.

14

FS3/PCI_F0

VDDP

I/O

PD

Power-on bidirectional Input/Output (I/O). At power-up, FS3 is the

input. When VTTPWRGD transitions to a logic HIGH, FS3 state is

latched and this pin becomes PCI_F0 clock output. See Table 1.

15

FS4/PCI_F1

VDDP

I/O

PD

Power-on bidirectional I/O. At power-up, FS4 is the input. When

VTTPWRGD transitions to a logic HIGH, FS4 state is latched and this

pin becomes PCI_F1 Clock Output. See Table 1.

2

FS0/REF0

VDDR

I/O

PD

Power-on bidirectional I/O. At power-up, FS0 is the input. When

VTTPWRGD transitions to a logic HIGH, FS0 state is latched and this

pin becomes REF0, buffered Output copy of the device’s XIN clock.

3

FS1/REF1

VDDR

I/O

PD

Power-on bidirectional I/O. At power-up, FS1 is the input. When

VTTPWRGD is transited to logic LOW, FS1 state is latched and this pin

becomes REF1, buffered Output copy of the device’s XIN clock.

4

FS2/REF2

VDDR

I/O

PD

Power-on bidirectional I/O. At power-up, FS2 is the input. When

VTTPWRGD is transited to logic LOW, FS2 state is latched and this pin

becomes REF2, buffered Output copy of the device’s XIN clock.

38

IREF

I

Current reference programming input for CPU buffers. A resistor is

connected between this pin and VSS. See Figure 8.

33

PD#/VTTPR

GD

I

PU

Power-down input/VTT power good input. At power-up, VTTPWRGD

is the input. When this input is transitions initially from LOW to HIGH,

the FS (0:4) and MULT0 are latched. After the first LOW-to-HIGH

transition, this pin becomes a PD# input with an internal pull-up. When

PD# is asserted LOW, the device enters power-down mode. See power

management function.

27

48M

VDD48M

O

Fixed 48-MHz USB clock output.

26

24_48M/MUL

T0

VDD48M

I/O

PU

Power-on bidirectional I/O. At power-up, MULT0 is the input. When

VTTPWRGD is transitions to logic HIGH MULT0 state is latched and this

pin becomes 24_48M, SIO programmable clock output.

9,10

ZCLK (0:1)

VDDZ

O

HyperZip Clock Outputs. See Table 1.

34

SDATA

I/O

Serial Data Input. Conforms to the SMBus specification of a Slave

Receive/Transmit device. It is an input when receiving data, and an open

drain output when acknowledging or transmitting data.

35

SCLK

I

Serial Clock Input. Conforms to the SMBus specification.

12

SRESET#

O

PCI Clock Disable Input. If Byte12 Bit7 = 0, this pin becomes an

SRESET# open drain output, and the internal pull-up is not active. See

system reset description.

PCI_STP#

I

PU

System Reset Control Output. If Byte12 Bit7 = 1 (Default), this pin

becomes PCI Clock Disable Input. When PCI_STP# is asserted LOW,

PCI (0:5) clocks are synchronously disabled in a LOW state. This pin

does not affect PCI_F (0:1) if they are programmed to be free-running

clocks via the device’s SMBus interface.

45

CPU_STP#

I

PU

CPU Clock Disable Input. When asserted LOW, CPU (0:1)T clocks are

synchronously disabled in a HIGH state and CPU (0:1)C clocks are

synchronously disabled in a LOW state.

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