CY28341-2

Rev 1.0, November 21, 2006

Page 6 of 18

Byte 2: PCI Clock Register

Bit

@Pup

Pin#

Name

Description

7

0

PCI_DRV

PCI clock output drive strength 0 = Low strength, 1 = High strength

6

1

10

PCI_F

1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.

5

1

18

PCI6

1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.

4

1

17

PCI5

1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.

3

1

15

PCI4

1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.

2

1

14

PCI3

1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.

1

1

12

PCI2

1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.

0

1

11

PCI1

1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.

Byte 3: AGP/Peripheral Clocks Register

Bit

@Pup

Pin#

Name

Description

70

21

24_48M

0 = pin21 output is 24 MHz. Writing a '1' into this register asynchronously

changes the frequency at pin21 to 48 MHz.

6

1

20

48MHz

1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.

5

1

21

24_48M

1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.

4

0

6,7,8

DASAG1

Programming these bits allow shifting skew of the AGP(0:2) signals relative to

their default value. See Table 5.

3

0

6,7,8

DASAG0

2

1

8

AGP2

1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.

1

1

7

AGP1

1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.

0

1

6

AGP0

1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.

Table 5. Dial-a-Skew

AGP(0:2)

DASAG (1:0)

AGP(0:2) Skew Shift

00

Default

01

–280 ps

10

+280 ps

11

+480 ps

Byte 4: Peripheral Clocks Register

Bit

@Pup

Pin#

Name

Description

7

1

20

48M

1 = Low strength, 0 = High strength

1 = strength x 1. 0= strength x 2

6

1

21

24_48M

1 = Low strength, 0 = High strength

1 = strength x 1. 0= strength x 2

5

0

6,7,8

DARAG1

Programming these bits allow modifying the frequency ratio of the AGP(2:0),

PCI(6:1, F) clocks relative to the CPU clocks. See Table 6.

4

0

6,7,8

DARAG0

3

1

1

REF0

1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.

2

1

56

REF1

1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.

1

1

1

REF0

1 = Low strength, 0 = High strength

0

1

56

REF1

1 = Low strength, 0 = High strength (K7 Mode only)

Table 6. Dial-A-Ratio

AGP(0:2)

DARAG (1:0)

CU/AGP Ratio

00

Frequency Selection Default

01

2/1

10

2.5/1

11

3/1