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CY28341ZC Datasheet(PDF) 1 Page - SpectraLinear Inc |
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CY28341ZC Datasheet(HTML) 1 Page - SpectraLinear Inc |
1 / 19 page Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems CY28341 Rev 1.0, November 20, 2006 Page 1 of 19 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 www.SpectraLinear.com Features • Supports VIA P4M266/KM266 chipsets • Supports Pentium® 4, Athlon™ processors • Supports two DDR DIMMS • Supports three SDRAMS DIMMS at 100 MHz • Provides: — Two different programmable CPU clock pairs — Six differential SDRAM DDR pairs — Three low-skew/low-jitter AGP clocks — Seven low-skew/low-jitter PCI clocks — One 48M output for USB — One programmable 24M or 48M for SIO • Dial-a-Frequency™ and Dial-a-dB features • Spread Spectrum for best electromagnetic interference (EMI) reduction • Watchdog feature for systems recovery • SMBus-compatible for programmability • 56-pin SSOP and TSSOP packages Note: 1. Pins marked with [*] have internal pull-up resistors. Pins marked with [**] have internal pull-down resistors. Table 1. Frequency Selection Table FS(3:0) CPU AGP PCI 0000 66.80 66.80 33.40 0001 100.00 66.80 33.40 0010 120.00 60.00 30.00 0011 133.33 66.67 33.33 0100 72.00 72.00 36.00 0101 105.00 70.00 35.00 0110 160.00 64.00 32.00 0111 140.00 70.00 35.00 1000 77.00 77.00 38.50 1001 110.00 73.33 36.67 1010 180.00 60.00 30.00 1011 150.00 60.00 30.00 1100 90.00 60.00 30.00 1101 100.00 66.67 33.33 1100 200.00 66.67 33.33 1111 133.33 66.67 33.33 BlockDiagram Pin Configuration[1] PLL1 S2D CONVERT SMBus WD CPUCS_T/C VDDC VDDI CPU(0:1)/CPU0D_T/C SELP4_K7# PCI(3:6) PCI_F FS1 REF(0:1) VDDR FS0 48M 24_48M FBOUT DDRT(0:5)/SDRAM(0,2,4,6,8,10) SCLK SDATA PD# AGP(0:2) VDDAGP VDD48M VDDD XTAL XOUT XIN FS2 PCI2 PCI1 VDDPCI PLL2 SRESET# / 2 Buf_IN REF0 FS3 MULTSEL SELSDR_DDR DDRC(0:5)/SDRAM(1,3,5,7,9,11) WDEN 56 pin SSOP VSSR *FS0/REF0 XIN XOUT VDDAGP AGP0 *SELP4_K7/AGP1 VSSAGP AGP2 **SELSDR_DDR/PCI1 *MULTSEL/PCI2 VSSPCI PCI3 PCI4 VDDPCI PCI5 PCI6 VSS48M **FS3/48M **FS2/24_48M VDD48M VDD VSS IREF *PD#/SRESET# SCLK SDATA **FS1/PCI_F VDDR VTTPWRGD#/REF1 VSSC CPUT/CPUOD_T CPUC/CPUOD_C VDDC VDDI CPUCS_T CPUCS_C FBOUT BUF_IN DDRT0/SDRAM0 DDRC0/SDRAM1 DDRT1/SDRAM2 DDRC1/SDRAM3 VDDD VSSD DDRT2/SDRAM4 DDRC2/SDRAM5 DDRT3/SDRAM6 DDRC3/SDRAM7 VDDD VSSD DDRT4/SDRAM8 DDRC4/SDRAM9 DDRT5/SDRAM10 DDRC5/SDRAM11 VSSI 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 2 3 4 5 6 7 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 |
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