Electronic Components Datasheet Search |
|
CY28339ZCT Datasheet(PDF) 6 Page - SpectraLinear Inc |
|
CY28339ZCT Datasheet(HTML) 6 Page - SpectraLinear Inc |
6 / 17 page CY28339 Rev 1.0, November 25, 2006 Page 6 of 17 Dial-a-Frequency Features SMBus Dial-a-Frequency feature is available in this device via Byte8 and Byte9. P is a large-value PLL constant that depends on the frequency selection achieved through the hardware selectors (S1, S0). P value may be determined from Table 2. Dial-a-dB Features SMBus Dial-a-dB feature is available in this device via Byte8 and Byte9. Spread Spectrum Clock Generation (SSCG) Spread Spectrum is a modulation technique used to minimizing EMI radiation generated by repetitive digital signals. A clock presents the greatest EMI energy at the center frequency it is generating. Spread Spectrum distributes this energy over a specific and controlled frequency bandwidth therefore causing the average energy at any one point in this band to decrease in value. This technique is achieved by modulating the clock away from its resting frequency by a certain percentage (which also determines the amount of EMI reduction). In this device, Spread Spectrum is enabled by setting specific register bits in the SMBus control bytes. Table 3 is a listing of the modes and percentages of Spread Spectrum modulation that this device incorporates. Special Functions PCIF and IOAPIC Clock Outputs The PCIF clock outputs are intended to be used, if required, for systems IOAPIC clock functionality. Any two of the PCIF clock outputs can be used as IOAPIC 33-Mhz clock outputs. They are 3.3V outputs will be divided down via a simple resistive voltage divider to meet specific system IOAPIC clock voltage requirements. In the event that these clocks are not required, they can be used as general PCI clocks or disabled via the assertion of the PCI_STOP# pin. 3V66_1/VCH Clock Output The 3V66_1/VCH pin has a dual functionality that is selectable via SMBus. Configured as DRCG (66M), SMBus Byte0, Bit 5 = “0” The default condition for this pin is to power-up in a 66M operation. In 66M operation this output is SSCG-capable and when spreading is turned on, this clock will be modulated. Configured as VCH (48M), SMBus Byte0, Bit 5 = “1” In this mode, output is configured as a 48-Mhz non-spread spectrum output that is phase-aligned with other 48M outputs (USB and DOT) to within 1-ns pin-to-pin skew. The switching of 3V66_1/VCH into VCH mode occurs at system power-on. When the SMBus Bit 5 of Byte 0 is programmed from a “0” to a “1,” the 3V66_1/VCH output may glitch while transitioning to 48M output mode. PD# (Power-down) Clarification The PD# (power-down) pin is used to shut off all clocks prior to shutting off power to the device. PD# is an asynchronous active LOW input. This signal is synchronized internally to the device powering down the clock synthesizer. PD# is an asynchronous function for powering up the system. When PD# is LOW, all clocks are driven to a LOW value and held there and the VCO and PLLs are also powered down. All clocks are shut down in a synchronous manner so has not to cause glitches while transitioning to the LOW “stopped” state. PD# Assertion When PD# is sampled LOW by two consecutive rising edges of the CPUC clock, then on the next HIGH-to-LOW transition of PCIF, the PCIF clock is stopped LOW. On the next HIGH-to-LOW transition of 66BUFF, the 66BUFF clock is stopped LOW. From this time, each clock will stop LOW on its next HIGH-to-LOW transition, except the CPUT clock. The CPU clocks are held with the CPUT clock pin driven HIGH with a value of 2 × Iref, and CPUC undriven. After the last clock has stopped, the rest of the generator will be shut down. Table 2. P Value S(1:0) P 0 0 32005333 0 1 48008000 1 0 96016000 1 1 64010667 Table 3. Spread Spectrum SS2 SS1 SS0 Spread Mode Spread% 0 0 0 Down +0.00, –0.25 0 0 1 Down +0.00, –0.50 0 1 0 Down +0.00, –0.75 0 1 1 Down +0.00, –1.00 1 0 0 Center +0.13, –0.13 1 0 1 Center +0.25, –0.25 1 1 0 Center +0.37, –0.37 1 1 1 Center +0.50, –1.50 Figure 1. Unbuffered Mode – 3V66_0 to PCI and PCIF Phase Relationship PCI PCI_F Tpci 3V66-0 |
Similar Part No. - CY28339ZCT |
|
Similar Description - CY28339ZCT |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |