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CY28339ZC Datasheet(PDF) 2 Page - SpectraLinear Inc |
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CY28339ZC Datasheet(HTML) 2 Page - SpectraLinear Inc |
2 / 17 page CY28339 Rev 1.0, November 25, 2006 Page 2 of 17 Pin Definitions Pin Number Name I/O Description 47 REF0 3.3V 14.318 MHz clock output. 1XIN 14.318 MHz crystal input. 2XOUT 14.318 MHz crystal input. 43, 42, 39, 38 CPUT1,CPUC1 CPUT2, CPUC2 Differential CPU clock outputs. 29 3V66_0 3.3V 66 MHz clock output. 31 3V66_1/VCH 3.3V selectable through SMBus to be 66 MHz or 48 MHz. 20 66IN/3V66_5 66 MHz input to buffered 66BUFF and PCI or 66 MHz clock from internal VCO. 17, 18, 19 66BUFF [2:0] /3V66 [4:2] 66 MHz buffered outputs from 66Input or 66 MHz clocks from internal VCO. 6PCIF 33 MHz clocks divided down from 66Input or divided down from 3V66; PCIF default is free-running. 8, 9, 10, 12, 13, 14, 4, 5 PCI [0:2] PCI [4:6] PCI [7:8] PCI clock outputs divided down from 66Input or divided down from 3V66; PCI [7:8] are configurable as free-running PCI through SMBus.[2] 35 USB_48M Fixed 48 MHz clock output. 34 DOT_48M Fixed 48 MHz clock output. 36 S2 Special 3.3V three-level input for Mode selection. 46 S1 3.3V LVTTL inputs for CPU frequency selection. 37 IREF A precision resistor is attached to this pin which is connected to the internal current reference. 21 PD# 3.3V LVTTL input for Power_Down# (active LOW). 30 PCI_STOP# 3.3V LVTTL input for PCI_STOP# (active LOW). 45 CPU_STOP# 3.3V LVTTL input for CPU_STOP# (active LOW). 24 VTT_PWRGD# 3.3V LVTTL input is a level-sensitive strobe used to determine when S[2:1] inputs are valid and OK to be sampled (Active LOW). Once VTT_PWRGD# is sampled LOW, the status of this input will be ignored. 25 SDATA SMBus-compatible SDATA. 26 SCLK SMBus-compatible SCLK. 11, 15, 28, 40, 44, 48 VDD_PCI, VDD_3V66, VDD_CPU,VDD_REF 3.3V power supply for outputs. 33 VDD_48 MHz 3.3V power supply for 48 MHz. 22 VDD_CORE 3.3V power supply for phase-locked loop (PLL). 3, 7, 16, 27, 32, 41 GND_REF, GND_PCI, GND_3V66, GND_IREF, GND_CPU Ground for outputs. 23 GND_CORE Ground for PLL. Note: 2. PCI3 is internally disabled and is not accessible. |
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