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CY28331 Datasheet(PDF) 5 Page - SpectraLinear Inc |
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CY28331 Datasheet(HTML) 5 Page - SpectraLinear Inc |
5 / 16 page CY28331 Rev 1.0, November 24, 2006 Page 5 of 16 0 1 13 PCI33_0 Enable (1 = Enabled, 0 = Disabled) Byte 2: USB, 24–48MHz, REF(0:2) Control Register Bit @Pup Pin # Name Description 7 active = 1 37, 36 CPUT/C(1) CPUT/C(1) shutdown. This bit can be optionally used to disable the CPUT/C(1) clock pair. During shutdown, CPUT = low and CPUC = high 6 active = 1 41, 40 CPUT/C(0) CPUT/C(0) shutdown. This bit can be optionally used to disable the CPUT/C(0) clock pair. During shutdown, CPUT = low and CPUC = high 5 active = 1 45 REF2 Enable (1 = Enabled, 0 = Disabled) 4 active = 1 48 REF1 Enable (1 = Enabled, 0 = Disabled) 3 active = 1 1 REF0 Enable (1 = Enabled, 0 = Disabled) 2 active = 1 28 24_48MHz Enable (1 = Enabled, 0 = Disabled) 1 active = 1 31 USB Enable (1 = Enabled, 0 = Disabled) 0 0 For Test, always program to ‘0’ Byte 3: PCI Clock Free Running Select Control Register Bit @Pup Pin # Name Description 7 Inactive = 0 PCI_DRV 0 = Low Strength 1 = High Strength 6 Inactive = 0 PCI33_HT66 Drive Strength 0 = Low Strength 1 = High Strength 5 Inactive = 0 22 PCI5 Free running enable (10 = Free running, 0 = Disabled) 4 Inactive = 0 21 PCI4 Free running enable (1 = Free running, 0 = Disabled) 3 Inactive = 0 18 PCI3 Free running enable (1 = Free running, 0 = Disabled) 2 1 11 PCI33_HT66_3 Enable (1 = Enabled, 0 = Disabled) 1 1 8 PCI33_HT66_2 Enable (1 = Enabled, 0 = Disabled) 0 1 7 PCI33_HT66_1 Enable (1 = Enabled, 0 = Disabled) Byte 4: Pin Latched/Real-time State Bit @Pup Pin# Name Description 7 1 6 PCI33_HT66_0 Enable (1 = Enabled, 0 = Disabled) 6 HW 24_48MHz/SEL# Pin power-up latched state 5 0 Reserved For Test, always program to ‘0’ 4 1 SSEN Spread Spectrum enable (0 = disable, 1 = enable). This bit provides a SW programmable control for spread spectrum clocking. 3 FS3 pin 31 FS3 Power-up latched state 2 FS2 pin 45 FS2 Power-up latched state 1 FS1 pin 48 FS1 Power-up latched state 0 FS0 pin 1 FS0 Power-up latched state Byte 1: PCI Clock Control Register (continued) Bit @Pup Pin# Name Description |
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