CY28326

Rev 1.0, November 20, 2006

Page 4 of 22

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer,

a two-signal serial interface is provided. Through the Serial

Data Interface, various device functions, such as individual

clock output buffers, can be individually enabled or disabled.

The registers associated with the Serial Data Interface

initializes to their default setting upon power-up, and therefore

use of this interface is optional. The interface can also be

accessed during power down operation.

Data Protocol

The clock driver serial protocol accepts byte write, byte read,

controller. For block write/read operation, the bytes must be

accessed in sequential order from lowest to highest byte (most

significant bit first) with the ability to stop after any complete

byte has been transferred. For byte write and byte read opera-

tions, the system controller can access individual indexed

bytes. The offset of the indexed byte is encoded in the

command code, as described in Table 4. The block write and

block read protocol is outlined in Table 5 while Table 6 outlines

the corresponding byte write and byte read protocol.The slave

receiver address is 11010010 (D2h).

Table 2. Mode Ratio Setting

Power-up Condition

Pin I/O Setting

Mode

RatioSel

Pin 19

Pin 20

0

x

PCI_STP#

CPU_STP#

0

x

PCI_STP#

CPU_STP#

1

0

Ratio0

Ratio1

1

1

PCI5

PCI6

Table 3. Ratio mapping Table

Power-up Frequency value

FS[1:0]

Ratio pin mapping

CPU

AGP

FS1

FS0

Pin 20

Pin 19

100

66.6

0

0

0

0

133

66.6

0

1

0

1

200

66.6

1

0

1

0

166

66.6

1

1

1

1

Table 4. Command Code Definition

Bit

Description

7

0 = Block read or block write operation

1 = Byte read or byte write operation

(6:5)

(4:0)

Device selection bits. Set = 00

Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'

Table 5. Block Read and Block Write protocol

Block Write Protocol

Block Read Protocol

Bit

Description

Bit

Description

1

Start

1

Start

8:2

Slave address – 7 bits

8:2

Slave address – 7 bits

9

Write

9

Write

10

Acknowledge from slave

10

Acknowledge from slave

18:11

Command Code – 8 Bits

18:11

Command Code – 8 Bits

19

Acknowledge from slave

19

Acknowledge from slave

27:20

Byte Count – 8 bits

20

Repeat start

28

Acknowledge from slave

27:21

Slave address – 7 bits

36:29

Data byte 1 – 8 bits

28

Read = 1

37

Acknowledge from slave

29

Acknowledge from slave

45:38

Data byte 2 – 8 bits

37:30

Byte Count from slave – 8 bits