CY28329

Rev 1.0, November 24, 2006

Page 3 of 16

S2

S1

CPU

(MHz)

3V66[0:1](

MHz)

66BUFF[0:2]/

3V66[2:4]

(MHz)

66IN/3V66_5

(MHz)

PCI_F/PCI

(MHz)

REF0(MHz)

USB/DOT

(MHz)

Notes

1

0

100 MHz

66 MHz

66IN

66-MHz Input

66IN/2

14.318 MHz

48 MHz

2, 3, 4

1

1

133 MHz

66 MHz

66IN

66-MHz Input

66IN/2

14.318 MHz

48 MHz

2, 3, 4

0

0

100 MHz

66 MHz

66 MHz

66-MHz Input

33 MHz

14.318 MHz

48 MHz

2, 3, 4

0

1

133 MHz

66 MHz

66 MHz

66-MHz Input

33 MHz

14.318 MHz

48 MHz

2, 3, 4

Mid

0

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

5, 6

Mid

1

TCLK/2

TCLK/4

TCLK/4

TCLK/4

TCLK/8

TCLK

TCLK/2

1, 6

Swing Select Functions

Mult0

Board Target

Trace/Term Z

Reference R, IREF =

Output

Current

0

50 ohm

Rr = 221 1%,

IREF = 5.00 mA

1.0V @ 50

1

50 ohm

Rr = 475 1%,

IREF = 2.32 mA

0.7V @ 50

Clock Driver Impedances

Buffer Name

Buffer Type

Impedance

Min.

(Ohm)

Typ.

(Ohm)

Max.

(Ohm)

CPU, CPU#

Type X1

50

REF

3.135–3.465

Type 3

20

40

60

PCI, 3V66, 66BUFF

3.135–3.465

Type 5

12

30

55

USB

3.135–3.465

Type 3A

12

30

55

DOT

3.135–3.465

Type 3B

12

30

55

Clock Enable Configuration

PD#

PCI_STOP#

CPU

CPU#

3V66

66BUFF

PCI_F

PCI

USB/DOT

VCOS/OSC

0

X

IREF*2

FLOAT

LOW

LOW

LOW

LOW

LOW

OFF

1

0

ON

ON

ON

ON

ON

OFF

ON

ON

1

1

ON

ON

ON

ON

ON

ON

ON

ON

Notes:

1. TCLK is a test clock driven in on the XTALIN input in test mode.

2. “Normal” mode of operation.

3. Range of reference frequency allowed is min. = 14.316 nominal = 14.31818 MHz, max. = 14.32 MHz.

4. Frequency accuracy of 48 MHz must be +167 PPM to match USB default.

5. Required for board level “bed of nails” testing.

6. Mid is defined a Voltage level between 1.0V and 1.8V for 3 level input functionality. Low is below 0.8V. High is above 2.0V.