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CY28329 Datasheet(PDF) 1 Page - SpectraLinear Inc |
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CY28329 Datasheet(HTML) 1 Page - SpectraLinear Inc |
1 / 16 page ![]() 133 MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs CY28329 Rev 1.0, November 24, 2006 Page 1 of 16 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 www.SpectraLinear.com Features • Multiple output clocks at different frequencies — Four pairs of differential CPU outputs, up to 133 MHz — Ten synchronous PCI clocks, three free-running — Six 3V66 clocks — Two 48-MHz clocks — One reference clock at 14.318 MHz — One VCH clock • Spread Spectrum clocking (down spread) • Power-down features (PCI_STOP#, PD#) • Three Select inputs (Mode select & IC Frequency Select) • OE and Test Mode support • 56-pin SSOP package and 56-pin TSSOP package Benefits • Motherboard clock generator — Support Multiple CPUs and a chipset — Support for PCI slots and chipset — Supports AGP and Hub Link — Supports USB host controller and graphic controller — Supports ISA slots and I/O chip • Enables reduction of EMI and overall system cost • Enables ACPI compliant designs • Supports up to four CPU clock frequencies • Enables ATE and “bed of nails” testing • Widely available, standard package enables lower cost Logic Block Diagram SSOP and TSSOP Top View 1 2 3 4 5 6 7 8 9 10 11 12 33 32 31 30 29 36 35 VDD_REF 34 13 14 15 16 17 18 19 20 21 22 23 24 45 44 43 42 41 37 38 39 40 48 47 46 XTAL_IN XTAL_OUT GND_REF 25 26 27 28 49 52 51 50 53 56 55 54 PCI0 PCI5 66BUFF2/3V66_4 GND_3V66 PCI_STOP# S2 GND_CPU CPU3# PCI_F2 GND_PCI GND_3V66 VDD_CORE VDD_ 48 MHz MULT0 VDD_CPU REF PCI_F0 PCI_F1 VDD_PCI GND_PCI PCI1 PCI2 PCI3 VDD_PCI PCI4 PCI6 VDD_3V66 66BUFF0/3V66_2 66BUFF1/3V66_3 66IN/3V66_5 PD# 3V66_0 VDD_3V66 3V66_1/VCH GND_ 48 MHz DOT USB GND_IREF IREF CPU2# CPU2 VDD_CPU CPU1# CPU1 CPU0# CPU0 CPU3 S1 GND_CORE VTTPWRGD# SCLK SDATA Pin Configurations VDD_REF CPU[0:3] CPU[0:3]# PCI_F[0:2] XTAL PLL Ref Freq X2 X1 REF VDD_PCI USB (48MHz) VCH_CLK/ 3V66_1 OSC VDD_CPU SCLK PCI0:6 PCI_STOP# Stop Clock Control PLL 1 SMBus Logic DOT (48MHz) PD# S1:2 VDD_48MHz SDATA VDD_3V66 3V66_0 3V66_[2:]4/ Divider Network 3V66_5/ 66IN PWR PWR PWR PWR PWR PLL 2 PWR 66BUFF0:2 Gate VTTPWRGD# /2 Mult0 |