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L4992 Datasheet(PDF) 7 Page - STMicroelectronics |
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L4992 Datasheet(HTML) 7 Page - STMicroelectronics |
7 / 26 page t t t 5V OSC 0V H5GATE H3GATE D97IN574 400ns min. Figure 1: Synchronization signal and operation. DETAILED FUNCTIONAL DESCRIPTION (continued) CLOCK S R Q Q _ REG5 HSTRAP L Rsense E.S. + - + - - + VREF SLOPE COMP. VIN Rf Cf Co ESR Ro Figure 2: L4992 Control Loop. The error summing, by comparing the above mentioned signals, determines the moment in which the output latch is to be reset. The high-side MOSFET is then turned off and the synchronous rectifier is turned on after the appropriate delay (typ. 75 ns), thus making the inductor current recirculate. This state is maintained until the next oscillator pulse. With reference to the schematic of fig. 2, the open-loop transfer function of such a kind of control system, under the assumption of an ideal slope compensation, is: F (s) = A⋅ RO Rsense ⋅ 1 + s ⋅ ESR ⋅ CO (1 + s ⋅ RO CO) ⋅ (1 + s ⋅ RF CF) where A is the gain of the error summing comparator, which is 2 by design. The system is inherently very fast since it tends to correct output voltage deviations nearly on a cycle-by- cycle basis. Actually, in case of line or load changes, few switching cycles can be sufficient for the tran- sient to expire. The operation above illustrated is modified during particular or anomalous conditions. Leaving out other circumstances (described in "Protections" section) for the moment, consider when the load current is low enough or during the first switching cycles at start-up: the inductor current may become discontinuous, that is it is zero during the last part of each cycle. In such a case, a "zero current comparator" detects the event and turns off the synchronous rectifier, avoiding inductor current reversal and reproducing the natural turn-off of a diode when reverse biased. Both MOSFET’s stay in off state until the next oscillator pulse. L4992 7/26 |
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