Dual/Quad Rail-to-Rail

Operational Amplifiers

OP295/OP495

Rev. E

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FEATURES

Rail-to-rail output swing

Single-supply operation: 3 V to 36 V

Low offset voltage: 300 μV

Gain bandwidth product: 75 kHz

High open-loop gain: 1000 V/mV

Unity-gain stable

Low supply current/per amplifier: 150 μA maximum

APPLICATIONS

Battery-operated instrumentation

Servo amplifiers

Actuator drives

Sensor conditioners

Power supply control

GENERAL DESCRIPTION

Rail-to-rail output swing combined with dc accuracy are the

key features of the OP495 quad and OP295 dual CBCMOS

operational amplifiers. By using a bipolar front end, lower noise

and higher accuracy than those of CMOS designs have been

achieved. Both input and output ranges include the negative

supply, providing the user with zero-in/zero-out capability. For

users of 3.3 V systems such as lithium batteries, the OP295/OP495

are specified for 3 V operation.

Maximum offset voltage is specified at 300 μV for 5 V operation,

and the open-loop gain is a minimum of 1000 V/mV. This yields

performance that can be used to implement high accuracy systems,

even in single-supply designs.

The ability to swing rail-to-rail and supply 15 mA to the load

makes the OP295/OP495 ideal drivers for power transistors and

H bridges. This allows designs to achieve higher efficiencies and

to transfer more power to the load than previously possible

without the use of discrete components.

For applications such as transformers that require driving

inductive loads, increases in efficiency are also possible.

Stability while driving capacitive loads is another benefit of this

design over CMOS rail-to-rail amplifiers. This is useful for

driving coax cable or large FET transistors. The OP295/OP495

are stable with loads in excess of 300 pF.

PIN CONFIGURATIONS

V+

8

OUT B

7

–IN B

6

+IN B

5

OP295

TOP VIEW

(Not to Scale)

Figure 1. 8-Lead Narrow-Body SOIC_N

(S Suffix)

OUT A

1

–IN A

2

+IN A

3

V–

4

V+

8

OUT B

7

–IN B

6

+IN B

5

OP295

Figure 2. 8-Lead PDIP

(P Suffix)

OUT A

1

–IN A

2

+IN A

3

V+

4

OUT D

14

–IN D

13

+IN D

12

V–

11

+IN B

5

–IN B

6

OUT B

7

+IN C

10

–IN C

9

OUT C

8

OP495

Figure 3. 14-Lead PDIP

(P Suffix)

OUT D

16

–IN D

15

+IN D

14

V–

13

+IN C

12

–IN C

11

OUT C

10

NC

9

NC = NO CONNECT

OP495

TOP VIEW

(Not to Scale)

Figure 4. 16-Lead SOIC_W

(S Suffix)

The OP295 and OP495 are specified over the extended indus-

trial (−40°C to +125°C) temperature range. The OP295 is

available in 8-lead PDIP and 8-lead SOIC_N surface-mount

packages. The OP495 is available in 14-lead PDIP and 16-lead

SOIC_W surface-mount packages.