CY28312B-2

Rev 1.0, November 21, 2006

Page 8 of 17

Byte 10: Skew Control Register

Bit

Name

Default

Description

Bit 7

CPU_Skew2

0

CPU skew control

000 = Normal

001 = –150 ps

010 = –300 ps

011 = –450 ps

100 = +150 ps

101 = +300 ps

110 = +450 ps

111 = +600 ps

Bit 6

CPU_Skew1

0

Bit 5

CPU_Skew0

0

Bit 4

Reserved

0

Reserved

Bit 3

PCI_Skew1

0

PCI skew control

00 = Normal

01 = –500 ps

10 = Reserved

11 = +500 ps

Bit 2

PCI_Skew0

0

Bit 1

AGP_Skew1

0

AGP skew control

00 = Normal

01 = –150 ps

10 = +150 ps

11 = +300 ps

Bit 0

AGP_Skew0

0

Byte 11: Recovery Frequency N–Value Register

Bit

Name

Default

Description

Bit 7

ROCV_FREQ_N7

0

If ROCV_FREQ_SEL is set, CY28312B-2 will use the values programmed in

ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery

CPU output frequency.when a Watchdog timer time-out occurs.

The setting of FS_Override bit determines the frequency ratio for CPU,

SDRAM, AGP and SDRAM. When it is cleared, CY28312B-2 will use the same

frequency ratio stated in the Latched FS[4:0] register. When it is set,

CY28312B-2 will use the frequency ratio stated in the SEL[4:0] register.

CY28312B-2 supports programmable CPU frequency ranging from 50 MHz to

248 MHz.

CY28312B-2 will change the output frequency whenever there is an update to

either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recom-

mended to use Word or Block write to update both registers within the same

SMBus bus operation.

Bit 6

ROCV_FREQ_N6

0

Bit 5

ROCV_FREQ_N5

0

Bit 4

ROCV_FREQ_N4

0

Bit 3

ROCV_FREQ_N3

0

Bit 2

ROCV_FREQ_N2

0

Bit 1

ROCV_FREQ_N1

0

Bit 0

ROCV_FREQ_N0

0

Byte 12: Recovery Frequency M–Value Register

Bit

Name

Default

Pin Description

Bit 7

ROCV_FREQ_SEL

0

ROCV_FREQ_SEL determines the source of the recover frequency when a

Watchdog timer time-out occurs. The clock generator will automatically switch

to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL.

0 = From latched FS[4:0]

1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0]

Bit 6

ROCV_FREQ_M6

0

If ROCV_FREQ_SEL is set, CY28312B-2 will use the values programmed in

ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery

CPU output frequency.when a Watchdog timer time-out occurs

The setting of FS_Override bit determines the frequency ratio for CPU,

SDRAM, AGP and SDRAM. When it is cleared, CY28312B-2 will use the same

frequency ratio stated in the Latched FS[4:0] register. When it is set,

CY28312B-2 will use the frequency ratio stated in the SEL[4:0] register.

CY28312B-2 supports programmable CPU frequency ranging from 50 MHz to

248 MHz.

CY28312B-2 will change the output frequency whenever there is an update to

either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recom-

mended to use Word or Block write to update both registers within the same

SMBus bus operation.

Bit 5

ROCV_FREQ_M5

0

Bit 4

ROCV_FREQ_M4

0

Bit 3

ROCV_FREQ_M3

0

Bit 2

ROCV_FREQ_M2

0

Bit 1

ROCV_FREQ_M1

0

Bit 0

ROCV_FREQ_M0

0