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CY28510 Datasheet(PDF) 9 Page - SpectraLinear Inc |
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CY28510 Datasheet(HTML) 9 Page - SpectraLinear Inc |
9 / 12 page CY28510 Rev 1.0, November 20, 2006 Page 9 of 12 CLK_STOP# Clarification The CLK_STOP# signal is an active low input used for synchronous stopping and starting the CLK output clocks while the rest of the clock generator continues to function. CLK_STOP# Assertion When CLK_STOP# pin is asserted low, all CLK outputs will be stopped after being sampled by two rising CLK internal clock edges. CLK_STOP# Deassertion The deassertion of the CLK_STOP# signal will cause all CLK outputs that were stopped to resume normal operation in a synchronous manner, synchronous manner meaning that no short or stretched clock pulses will be produced when the clock resumes. The maximum latency from the deassertion to active outputs is no more than 2 CLK clock cycles 2.0 V VD D _ AL L CL K RE F <1 .2 m s e c Figure 3. Power-up Signal Timing CLK_STOP# CLK CLK Internal Figure 4. CLK_STOP# Assertion Waveforms CLK_STOP# CLK CLK Internal Figure 5. CLK_STOP# Deassertion Waveforms |
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