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CY2SSTV16859LFIT Datasheet(PDF) 1 Page - SpectraLinear Inc |
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CY2SSTV16859LFIT Datasheet(HTML) 1 Page - SpectraLinear Inc |
1 / 7 page 13-Bit to 26-Bit Registered Buffer PC2700-/PC3200-Compliant CY2SSTV16859 Rev 1.0, November 21, 2006 Page 1 of 7 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 www.SpectraLinear.com Features • Differential clock inputs up to 280 MHz • Supports LVTTL switching levels on the RESET# pin • Output drivers have controlled edge rates, so no external resistors are required. • Two KV ESD protection • Latch-up performance exceeds 100 mA per JESD78, Class II • 64-pin TSSOP/JEDEC and 56-pin QFN package avail- ability • JEDEC specification supported Description This 13-bit to 26-bit registered buffer is designed for 2.3V to 2.7 VDD operations. All inputs are compatible with the JEDEC Standard for SSTL-2, except the LVCMOS reset (RESET#) input. All outputs are SSTL_2, Class II compatible. The CY2SSTV16859 operates from a differential clock (CLK and CLK#) of frequency up to 280 MHz. Data are registered at crossing of CLK going high and CLK# going low. When RESET# is low, the differential input receivers are disabled, and undriven (floating) data and clock inputs are allowed. The LVCMOS RESET# input must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET# must be held in the low state during power up. In the DDR DIMM application, RESET# is completely asynchronous with respect to CLK# and CLK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register is cleared and the outputs are driven low quickly, relative to the time to disable the differential input receivers, thus ensuring no glitches on the output. However, when coming out of reset, the register becomes active quickly, relative to the time to enable the differential input receivers. Block Diagram Pin Configuration D1 VREF CLK # Q1A Q1B To 12 Other Channels CLK RESET # D C R 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Q13A Q12A Q11A Q10A Q9A VDDQ GND Q8A Q7A Q6A Q5A Q4A Q3A Q2A GND Q1A Q13B VDDQ Q12B Q11B Q10B Q9B Q8B Q7B Q6B GND VDDQ Q5B Q4B Q3B Q2B Q1B 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDDQ GND D13 D12 VDD VDDQ GND D11 D10 D9 GND D8 D7 RESET # GND CLK # CLK VDDQ VDD VREF D6 GND D5 D4 D3 GND VDDQ VDD D2 D1 GND VDDQ |
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