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CY28RS600ZXC Datasheet(PDF) 4 Page - SpectraLinear Inc |
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CY28RS600ZXC Datasheet(HTML) 4 Page - SpectraLinear Inc |
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4 / 17 page  CY28RS600 Rev 1.0, November 22, 2006 Page 4 of 17 Control Registers .... Data Byte N – 8 bits 47 Acknowledge .... Acknowledge from slave 55:48 Data byte 2 from slave – 8 bits .... Stop 56 Acknowledge .... Data bytes from slave/Acknowledge .... Data Byte N from slave – 8 bits .... NOT Acknowledge Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Byte Read Protocol Bit Description Bit Description 1Start 1Start 8:2 Slave address–7 bits 8:2 Slave address–7 bits 9Write 9Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code–8 bits 18:11 Command Code–8 bits 19 Acknowledge from slave 19 Acknowledge from slave 27:20 Data byte–8 bits 20 Repeated start 28 Acknowledge from slave 27:21 Slave address–7 bits 29 Stop 28 Read 29 Acknowledge from slave 37:30 Data from slave–8 bits 38 NOT Acknowledge 39 Stop Table 3. Block Read and Block Write Protocol (continued) Block Write Protocol Block Read Protocol Bit Description Bit Description Byte 0: Output Enable Register 0 Bit @Pup Name Description 7 1 SRC[T/C]7 SRC[T/C]7 Output Enable 0 = Disable (Hi-Z), 1 = Enable 6 1 SRC[T/C]6 SRC[T/C]6 Output Enable 0 = Disable (Hi-Z), 1 = Enable 5 1 SRC[T/C]5 SRC[T/C]5 Output Enable 0 = Disable (Hi-Z), 1 = Enable 4 1 SRC[T/C]4 SRC[T/C]4 Output Enable 0 = Disable (Hi-Z), 1 = Enable 3 1 SRC[T/C]3 SRC[T/C]3 Output Enable 0 = Disable (Hi-Z), 1 = Enable 2 1 SRC[T/C]2 SRC[T/C]2 Output Enable 0 = Disable (Hi-Z), 1 = Enable 1 1 SRC[T/C]1 SRC[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enable 0 1 SRC [T/C]0 SRC[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enable |
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