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CY2SSTV855ZXI Datasheet(PDF) 5 Page - SpectraLinear Inc |
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CY2SSTV855ZXI Datasheet(HTML) 5 Page - SpectraLinear Inc |
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5 / 6 page  CY2SSTV855 Rev 1.0, November 21, 2006 Page 5 of 6 Absolute Maximum Conditions[3] Input Voltage Relative to VSS:...............................VSS – 0.3V Input Voltage Relative to VDDQ or AVDD: ............. VDD + 0.3V Storage Temperature: ................................ –65 C to + 150 C Operating Temperature:................................ –40 C to +85 C Maximum Power Supply: ................................................ 3.5V This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS < (Vin or Vout) < VDD. Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). DC Electrical Specifications (AVDD = VDDQ = 2.5V ± 5%, TA = –40°C to +85°C) [4] Parameter Description Conditions Min. Typ. Max. Unit VID Differential Input Voltage[5] CLKINT, FBINT 0.36 VDDQ + 0.6 V VIX Differential Input Crossing Voltage[6] CLKTIN, FBINT (VDDQ/2) – 0.2 VDDQ/2 (VDDQ/2) + 0.2 V IIN Input Current VIN = 0V or VIN = VDDQ, CLKINT, FBINT –10 – 10 µA IOL Output Low Current VDDQ = 2.375V, VOUT = 1.2V 26 35 – mA IOH Output High Current VDDQ = 2.375V, VOUT = 1V –18 –32 – mA VOL Output Low Voltage VDDQ = 2.375V, IOL = 12 mA – 0.6 V VOH Output High Voltage VDDQ = 2.375V, IOH = –12 mA 1.7 – – V VOUT Output Voltage Swing[7] 1.1 – VDDQ – 0.4 V VOC Output Crossing Voltage[8] (VDDQ/2) – 0.2 VDDQ/2 (VDDQ/2) + 0.2 V IOZ High-Impedance Output Current VO = GND or VO = VDDQ –10 10 µA IDDQ Dynamic Supply Current[9] VDDQ = 170 MHz – 235 300 mA IDD PLL Supply Current AVDD only – 9 12 mA Cin Input Pin Capacitance – 4 – pF AC Electrical Specifications (AVDD = VDDQ = 2.5V±5%, TA = –40°C to +85°C) [10, 11] Parameter Description Conditions Min. Typ. Max. Unit fCLK Operating Clock Frequency AVDD = 2.5V 0.2V 60 170 MHz tDC Input Clock Duty Cycle[12] 40 60 % tLOCK Maximum PLL lock Time 100 µs tSL(O) Output Clocks Slew Rate 20% to 80% of VOD 1 2 V/ns tPZL, tPZH Output Enable Time (all outputs)[13] 30 ns tPLZ, tPHZ Output Disable Time (all outputs)[13] 10 ns tCCJ Cycle to Cycle Jitter f > 66 MHz –100 100 ps tJITT(H-PER) Half-period jitter f > 66 MHz –100 100 ps Notes: 3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 4. Unused inputs must be held HIGH or LOW to prevent them from floating. 5. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level and VCP is the comple- mentary input level. 6. Differential cross-point input voltage is expected to track VDDQ and is the voltage at which the differential signals must be crossing. 7. For load conditions see Figure 6. 8. The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120 resistor. See Figure 6. 9. All outputs switching loaded with 16 pF in 60 environment. See Figure 6. 10. Parameters are guaranteed by design and characterization. Not 100% tested in production. 11. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 33.3 kHz with a downspread of –0.5% 12. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = tWH/tC, where the cycle time (tC) decreases as the frequency goes up. 13. Refers to transition of non-inverting output. 14. All differential input and output terminals are terminated with 120 /16 pF as shown in Figure 6. |
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