Differential Clock Buffer/Driver DDR333/PC2700-Compliant

CY2SSTV857-27

Rev 1.0, November 21, 2006

Page 1 of 8

2200 Laurelwood Road, Santa Clara, CA 95054

Tel:(408) 855-0555

Fax:(408) 855-0550

www.SpectraLinear.com

Features

• Operating frequency: 60 MHz to 200 MHz

• Supports 266, 333 MHz DDR SDRAM

• 10 differential outputs from 1 differential input

• Spread-Spectrum-compatible

• Low jitter (cycle-to-cycle): < 75

• Very low skew: < 100 ps

• Power management control input

• High-impedance outputs when input clock < 10 MHz

• 2.5V operation

• Pin-compatible with CDC857-2 and -3

• 48-pin TSSOP package

• Industrial temp. of –40° to +85°C

• Conforms to JEDEC DDR specification

Description

The CY2SSTV857-27 is a high-performance, low-skew,

low-jitter zero-delay buffer designed to distribute differential

clocks in high-speed applications. The CY2SSTV857-27

generates ten differential pair clock outputs from one differ-

ential pair clock input. In addition, the CY2SSTV857-27

features differential feedback clock outputs and inputs. This

allows the CY2SSTV857-27 to be used as a zero-delay buffer.

When used as a zero-delay buffer in nested clock trees, the

CY2SSTV857-27 locks onto the input reference and translates

with near-zero delay to low-skew outputs.

Block Diagram

Pin Configuration

3

2

5

6

10

9

20

19

22

23

46

47

44

43

39

40

29

30

27

26

32

33

Y0

Y0 #

Y1

Y1 #

Y2

Y2 #

Y3

Y3 #

Y4

Y4 #

Y5

Y5 #

Y6

Y6 #

Y7

Y7 #

Y8

Y8 #

Y9

Y9 #

FB O U T

FB O U T #

T e s t and

Po w e rd o w n

Log ic

PL L

13

14

36

35

FB IN

FB IN #

CL K

CL K #

AV D D

37

16

PD #

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

VSS

Y0 #

Y0

VD D Q

Y1

Y1 #

VSS

VSS

Y2 #

Y2

VD D Q

VD D Q

CL K

CL K #

VD D Q

AVD D

AVSS

VSS

Y3 #

Y3

VD D Q

Y4

Y4 #

VSS

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

VSS

Y5 #

Y5

V DDQ

Y6

Y6 #

VSS

VSS

Y7 #

Y7

V DDQ

PD #

FB IN

FB IN #

VD D Q

FB O U T #

FB O U T

VSS

Y8 #

Y8

V DDQ

Y9

Y9 #

VSS