CY2SSTU877

Rev 1.0, November 21, 2006

Page 7 of 8

CLKT/CLKC

CLKT

CLKC

Figure 8. Output Enable and Disable Times

Figure 9. Input/Output Slew Rates

CLKT

CLKC

PLL

AVDD

AGND

0.1

µF

2200 pF

4.7 pF

R1

CARD

VIA

CARD

VIA

VDDQ

GND

Bead

1206

0603

0603

[3,4,5]

Ordering Information

Part Number

Package Type

Product Flow

Lead-free and ROHS Compliant

CY2SSTU877BVXC-32

52-pin VFBGA for DDR400

Commercial, 0 to 70 C

CY2SSTU877BVXC-32T

52-pin VFBGA for DDR400 – Tape& Reel Commercial, 0 to 70 C

CY2SSTU877BVXI-32

52-pin VFBGA for DDR400

Industrial, –40 to 85 C

CY2SSTU877BVXI-32T

52-pin VFBGA for DDR400 – Tape& Reel Industrial, –40 to 85 C

CY2SSTU877BVXC-43

52-pin VFBGA for DDR533

Commercial, 0 to 70 C

CY2SSTU877BVXC-43T

52-pin VFBGA for DDR533 – Tape& Reel Commercial, 0 to 70 C

CY2SSTU877BVXI-43

52-pin VFBGA for DDR533

Industrial, –40 to 85 C

CY2SSTU877BVXI-43T

52-pin VFBGA for DDR533 – Tape& Reel Industrial, –40 to 85 C

Notes:

3. Place the 2200-pF capacitor close to the PLL.

4. Use a wide trace for the PLL analog power and ground. Connect PLL & Caps to AGND trace & connect trace to one GND via (farthest from PLL).

5. Recommended bead: Fair-Rite P/N 2506036017Y0 or equivalent (0.9 ohm DC max, 600 ohms@100 MHz).