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ADN4667ARUZ-REEL7 Datasheet(PDF) 11 Page - Analog Devices

Part # ADN4667ARUZ-REEL7
Description  3 V LVDS Quad CMOS Differential Line Driver
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADN4667ARUZ-REEL7 Datasheet(HTML) 11 Page - Analog Devices

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ADN4667
Rev. 0 | Page 11 of 12
THEORY OF OPERATION
The ADN4667 is a quad line driver for low voltage differential
signaling. It takes a single-ended 3 V logic signal and converts
it to a differential current output. The data can then be trans-
mitted for considerable distances, over media such as a twisted
pair cable or PCB backplane, to an LVDS receiver, where it devel-
ops a voltage across a terminating resistor, RT. This resistor is
chosen to match the characteristic impedance of the medium,
typically around 100 Ω. The differential voltage is detected by
the receiver and converted back into a single-ended logic signal.
When DIN is high (Logic 1), current flows out of the DOUT+
pin (current source) through RT and back into the DOUT− pin
(current sink). At the receiver, this current develops a positive
differential voltage across RT (with respect to the inverting
input) and gives a Logic 1 at the receiver output. When DIN is
low, DOUT+ sinks current and DOUT− sources current; a negative
differential voltage across RT gives a Logic 0 at the receiver
output.
The output drive current is between ±2.5 mA and ±4.5 mA
(typically ±3.1 mA), developing between ±250 mV and ±450 mV
across a 100 Ω termination resistor. The received voltage is
centered around the receiver offset of 1.2 V. In other words, the
noninverting receiver input is typically (1.2 V + [310 mV/2]) =
1.355 V, and the inverting receiver input is (1.2 V − [310 mV/2]) =
1.045 V for Logic 1. For Logic 0, the inverting and noninverting
output voltages are reversed. Note that because the differential
voltage reverses polarity, the peak-to-peak voltage swing across
RT is twice the differential voltage.
Current-mode drivers offer considerable advantages over
voltage-mode drivers such as RS-422 drivers. The operating
current remains fairly constant with increased switching
frequency, whereas that of voltage-mode drivers increases
exponentially in most cases. This is caused by the overlap
as internal gates switch between high and low, which causes
currents to flow from the device power supply to ground.
A current-mode device simply reverses a constant current
between its two outputs, with no significant overlap currents.
This is similar to emitter-coupled logic (ECL) and positive
emitter-coupled logic (PECL), but without the high quiescent
current of ECL and PECL.
ENABLE INPUTS
The ADN4667 has active high and active low enable inputs,
which deactivate all the current drivers when in the disabled
state. This also powers down the device and reduces the current
consumption from typically 20 mA to typically 2.2 mA. A truth
table for the enable inputs is shown in Table 5.
Table 5. Enable Inputs Truth Table
EN
EN
DIN
DOUT+
DOUT−
H
L or open
L
ISINK
ISOURCE
H
L or open
H
ISOURCE
ISINK
Any other combination of EN and EN
X
Inactive
Inactive
APPLICATIONS INFORMATION
Figure 24 shows a typical application for point-to-point data
transmission.
DIN
DOUT
RT
100Ω
EN
EN
1/4 ADN4667
RECEIVER
Figure 24. Typical Application Circuit


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