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AD7991 Datasheet(PDF) 4 Page - Analog Devices

Part No. AD7991
Description  4-Channel, 12-/10-/8-Bit ADC with I2C-Compatible Interface in 8-Lead SOT-23
Download  28 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD7991 Datasheet(HTML) 4 Page - Analog Devices

 
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AD7991/AD7995/AD7999
Rev. 0 | Page 4 of 28
Y Version
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LOGIC INPUTS (SDA, SCL)
Input High Voltage, VINH
0.7 (VDD)
V
VDD = 2.7 V to 5.5 V
0.9 (VDD)
V
VDD = 2.35 V to 2.7 V
Input Low Voltage, VINL
0.3 (VDD)
V
VDD = 2.7 V to 5.5 V
0.1 (VDD)
V
VDD = 2.35 V to 2.7 V
Input Leakage Current, IIN
±1
μA
VIN = 0 V or VDD
Input Capacitance, CIN6
10
pF
Input Hysteresis, VHYST
0.1 (VDD)
V
LOGIC OUTPUTS (OPEN DRAIN)
Output Low Voltage, VOL
0.4
V
ISINK = 3 mA
0.6
V
ISINK = 6 mA
Floating-State Leakage Current
±1
μA
Floating-State Output Capacitance6
10
pF
Output Coding
Straight (natural) binary
THROUGHPUT RATE
18 × (1/fSCL)
fSCL ≤ 1.7 MHz; see the
Serial Interface section
17.5 × (1/fSCL)
+ 2 μs
fSCL > 1.7 MHz; see the
Serial Interface section
POWER REQUIREMENTS2
VREF = VDD; for fSCL = 3.4 MHz,
clock stretching is implemented
VDD
2.7
5.5
V
IDD
Digital inputs = 0 V or VDD
ADC Operating, Interface Active
(Fully Operational)
0.09/0.25
mA
VDD = 3.3 V/5.5 V, 400 kHz fSCL
0.25/0.8
mA
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL
Power-Down, Interface Active7
0.07/0.16
mA
VDD = 3.3 V/5.5 V, 400 kHz fSCL
0.26/0.85
mA
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL
Power-Down, Interface Inactive7
1/1.6
μA
VDD = 3.3 V/5.5 V
Power Dissipation
ADC Operating, Interface Active
(Fully Operational)
0.3/1.38
mW
VDD = 3.3 V/5.5 V, 400 kHz fSCL
0.83/4.4
mW
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL
Power-Down, Interface Active7
0.24/0.88
mW
VDD = 3.3 V/5.5 V, 400 kHz fSCL
0.86/4.68
mW
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL
Power-Down, Interface Inactive7
3.3/8.8
μW
VDD = 3.3 V/5.5 V
1 Functional from VDD = 2.35 V.
2 Sample delay and bit trial delay enabled, t1 = t2 = 0.5/fSCL.
3 For fSCL up to 400 kHz, clock stretching is not implemented. Above fSCL = 400 kHz, clock stretching is implemented.
4 See the Terminology section.
5 For fSCL ≤ 1.7 MHz, clock stretching is not implemented; for fSCL > 1.7 MHz, clock stretching is implemented.
6 Guaranteed by initial characterization.
7 See the Reading from the AD7991/AD7995/AD7999 section.


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