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FPD2250SOT89 Datasheet(PDF) 2 Page - Filtronic Compound Semiconductors

Part No. FPD2250SOT89
Description  LOW NOISE HIGH LINEARITY PACKAGED PHEMT
Download  6 Pages
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Maker  FILTRONIC [Filtronic Compound Semiconductors]
Homepage  http://www.filtronic.co.uk/
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FPD2250SOT89 Datasheet(HTML) 2 Page - Filtronic Compound Semiconductors

   
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Specifications subject to change without notice
Filtronic Compound Semiconductors Ltd
Tel: +44 (0) 1325 301111
Fax: +44 (0) 1325 306177
Email: sales@filcs.com
Website: www.filtronic.com
2
Datasheet v3.0
FPD2250SOT89
ABSOLUTE MAXIMUM RATING1:
Notes:
PARAMETER
SYMBOL
TEST CONDITIONS
ABSOLUTE MAXIMUM
Drain-Source Voltage
VDS
-3V < VGS < +0V
8V
Gate-Source Voltage
VGS
0V < VDS < +8V
-3V
Drain-Source Current
IDS
For VDS < 2V
IDss
Gate Current
IG
Forward or reverse current
22mA
RF Input Power
2
PIN
Under any acceptable bias state
525mW
Channel Operating Temperature
TCH
Under any acceptable bias state
175°C
Storage Temperature
TSTG
Non-Operating Storage
-55°C to 150°C
Total Power Dissipation
PTOT
See De-Rating Note below
2.5W
Gain Compression
Comp.
Under any bias conditions
5dB
Simultaneous Combination of Limits
3
2 or more Max. Limits
1TAmbient = 22°C unless otherwise noted; exceeding any one of these absolute maximum ratings may cause
permanent damage to the device
2Max. RF Input Limit must be further limited if input VSWR > 2.5:1
3Users should avoid exceeding 80% of 2 or more Limits simultaneously
4Total Power Dissipation defined as: PTOT ≡ (PDC + PIN) – POUT,
where PDC: DC Bias Power, PIN: RF Input Power, POUT: RF Output Power
Total Power Dissipation to be de-rated as follows above 22
°C:
PTOT= 2.5 - (0.02W/°C) x TPACK
where TPACK= source tab lead temperature above 22°C
(coefficient of de-rating formula is the Thermal Conductivity)
Example: For a 65
°C carrier temperature: PTOT = 2.5W – (0.02 x (65 – 22)) = 1.64W
BIASING GUIDELINES:
Active bias circuits provide good performance stabilization over variations of operating
temperature, but require a larger number of components compared to self-bias or dual-biased.
Such circuits should include provisions to ensure that Gate bias is applied before Drain bias,
otherwise the pHEMT may be induced to self-oscillate
Dual-bias circuits are relatively simple to implement, but will require a regulated negative voltage
supply for depletion-mode devices.
For standard class A operation, a 50% of IDSS bias point is recommended. A small amount of
RF gain expansion prior to the onset of compression is normal for this operating point. A class
A/B bias of 25-33% of IDSS to achieve better OIP3 and Noise Figure performance is suggested.


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