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TH8062 Datasheet(PDF) 10 Page - Melexis Microelectronic Systems |
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TH8062 Datasheet(HTML) 10 Page - Melexis Microelectronic Systems |
10 / 38 page TH8062 Voltage Regulator with LIN Transceiver TH8062 – Datasheet Page 10 of 38 3901008062 March 2006 Rev 002 Parameter Symbol Condition Min Typ Max Unit T [1] LIN transceiver parameter according to LIN Physical Layer Spec. rev. 2.0, table 3.4 (20kbit/s) Conditions: Normal slew mode; VSUP =7.0V to 18V; BUS loads: 1k Ω/1nF; 660Ω/6.8nF; 500Ω/10nF TxD signal: tBit = 50µs, twH = TwL = tBit; trise = tfall < 100ns Minimal recessive bit time [2] trec(min) 40 50 58 µs Maximum recessive bit time [2] trec(max) 40 50 58 µs Duty cycle 1 D1 D1 = trec(min) / (2*tBit) 0.396 A Duty cycle 2 D2 D2 = trec(max) / (2*tBit) 0.581 A LIN transceiver parameter according to LIN Physical Layer Spec. rev. 2.0, table 3.4 (10.4kbit/s) Conditions: Low slew mode; VSUP =7.0V to 18V; BUS loads: 1k Ω/1nF; 660Ω/6.8nF; 500Ω/10nF TxD signal: tBit = 96µs, twH = TwL = tBit; trise = tfall < 100ns Minimal recessive bit time [2] trec(min) 80 96 113 µs Maximum recessive bit time [2] trec(max) 80 96 113 µs Duty cycle 1 D1 D1 = trec(min) / (2*tBit) 0.417 A Duty cycle 2 D2 D2 = trec(max) / (2*tBit) 0.590 A LIN transceiver parameter according to SAE J2602 (10.4kbit/s) Conditions: Low slew mode; VSUP =7.0V to 18V; BUS loads: 1k Ω/1nF;660Ω/6.8nF;500Ω/10nF TxD signal: tBit = 96µs, twH = TwL = tBit; trise = tfall < 100ns Minimal recessive delay TxD -> BUS [2] tx_rec_min 48 µs Maximum recessive delay TxD -> BUS [2] tx_rec_max 48 µs Minimal dominant delay TxD -> BUS [2] tx_dom_min 48 µs Maximum dominant delay TxD -> BUS [2] tx_dom_max 48 µs Maximum rec. to dom. delay Tr_d_max tx_rec_max - tx_dom_min 15.9 µs A Maximum dom. to rec. delay Td_r_max tx_dom_max - tx_rec_min 17.2 µs A [1] A = 100% serial test, B = Operating parameter, C = only used for data characterization (cpk), D = Value guaranteed by design [2] See chapter 2.5 Timing Diagrams |
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