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ISL8012IRZ Datasheet(PDF) 6 Page - Intersil Corporation |
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ISL8012IRZ Datasheet(HTML) 6 Page - Intersil Corporation |
6 / 15 page 6 FN6616.0 March 11, 2008 Pin Descriptions VIN (Pin 1) Input supply voltage. Connect a 10µF ceramic capacitor to power ground. VCC (Pin 2) Input supply for the logic. Connect to VIN. EN (Pin 3) Regulator enable pin. Enable the output when driven to high. Shutdown the chip and discharge output capacitor when driven to low. Do not leave this pin floating. PG (Pin 4) 1ms timer output. At power-up or EN HI, this output is a 1ms delayed Power-Good signal for the output voltage. This output can be reset by a low RSI signal. 1ms starts when RSI goes to high. MODE (Pin 5) Mode Selection pin. Connect to logic high or input voltage VIN for PFM mode; connect to logic low or ground for forced PWM mode. Do not leave this pin floating. RSI (Pin 6) This input resets the 1ms timer. When the output voltage is within the PGOOD window, an internal timer is started and generates a PG signal 1ms later when RSI is low. A high RSI resets PG and RSI high to low transition restarts the internal counter if the output voltage is within the window, otherwise the counter is reset by the output voltage condition. VFB (Pin 7) Buck regulator output feedback. Connect to the output through a resistor divider for adjustable output voltage (ISL8012-ADJ). For preset output voltage, connect this pin to the output. SGND (Pin 8) System ground for the control logic. All voltage levels are measured with respect to this pin. PGND (Pin 9) Ground connect for the IC and thermal relief for the package. The exposed pad must be connected to PGND and soldered to the PCB. LX (Pin 10) Switching node connection. Connect to one terminal of inductor. Exposed Pad The exposed pad must be connected to the PGND and SGND pin for proper electrical performance. The exposed pad must also be connected to as much as possible for optimal thermal performance. ISL8012 |
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