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HCF4033BEY Datasheet(PDF) 2 Page - STMicroelectronics |
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HCF4033BEY Datasheet(HTML) 2 Page - STMicroelectronics |
2 / 15 page cade counter to its zero count. The counter is ad- vanced one count at the positive clock signal tran- sition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT signal is high. Antilock gating is provided on the JOHNSON counter, thus assuring proper counting sequence. The CARRY-OUT (Cout) signal completes one cycle every ten CLOCK INPUT cycles and is used to clock the succeeding decade directly in a multi-decade counting chain. The seven decoded outputs (a, b, c, d, e, f, g) illumi- nate the proper segments in a seven segment dis- play device used for representing the decimal numbers 0 to 9. The 7-segment outputs go high on selection in the HCC/HCF4033B ; in the HCC/- HCF4026B these outputs go high only when the DISPLAY ENABLE IN is high. HCC/HCF4026B - When the DISPLAY ENABLE IN is low the seven decoded outputs are forced low re- gardless of the state of the counter. Activation of the display only when required results in significant power savings. This system also facilitates im- plementation of display-character multiplexing. The CARRY OUT and UNGATED ”C-SEGMENT” sig- nals are not gated by the DISPLAY ENABLE and therefore are available continuously. This feature is a requirement in implementation of certain divider functions such as divide-by-60 and divide-by-12. HCC/HCF4033B -The HCC/HCF4033B has provi- sions for automatic blanking of the non-significant zeros in a multi-digit decimal number which results in an easily readable display consistent with normal writing practice. For example, the number 0050.07000 in an eight digit display would be dis- played as 50.07. Zero suppression on the integer side is obtained by connecting the RBI terminal of the HCC/HCF4033B associated with the most sig- nificant digit in the display to a low-level voltage and connecting the RBO terminal of that stage to the RBI terminal of the HCC/HCF4033B in the next-lower significant position in the display. This procedure is continued for each succeeding HCC/HCF4033B on the integer side of the display. On the fraction side of the display the RBI of the HCC/HCF4033B asso- ciated with the least significant bit is connected to a low-level voltage and the RBO of that HCC/- HCF4033B is connected to the RBI terminal of the HCC/HCF4033B in the next more-significant-bit po- sition. Again, this procedure is continued for all HCC/HCF4033B’s on the fraction side of the dis- play. In a purely fractional number the zero immedi- ately preceding the decimal point can be displayed by connecting the RBI of that stage to a high level voltage (instead of to the RBO of the next more-sig- nificant-stage). For example : optional zero → 0.7346. Likewise, the zero in a number such as 763.0 can be displayed by connecting the RBI of the HCC/HCF4033B associated with it to a high-level voltage. Ripple blanking of non-significant zeros provides an appreciable savings in display power. The HCC/HCF4033B has a LAMP TEST input which, when connected to a high-level voltage, overrides normal decoder operation and enables a check to be made on possible display malfunctions by putting the seven outputs in the high state. HCC/HCF4026B/4033B 2/15 |
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