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843301BGI-108T Datasheet(PDF) 8 Page - Integrated Device Technology |
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843301BGI-108T Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 15 page IDT™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC 8 ICS843301BGI-108 REV. A OCTOBER 9, 2007 ICS843301I-108 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC PRELIMINARY V CC - 2V 50 Ω 50 Ω RTT Z o = 50Ω Z o = 50Ω FOUT FIN RTT = Z o 1 ((V OH + VOL) / (VCC – 2)) – 2 3.3V 125 Ω 125 Ω 84 Ω 84 Ω Z o = 50Ω Z o = 50Ω FOUT FIN The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that gen- erate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock lay- outs may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. TERMINATION FOR 3.3V LVPECL OUTPUT FIGURE 5B. LVPECL OUTPUT TERMINATION FIGURE 5A. LVPECL OUTPUT TERMINATION |
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