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ICS1523MLF Datasheet(PDF) 10 Page - Integrated Device Technology |
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ICS1523MLF Datasheet(HTML) 10 Page - Integrated Device Technology |
10 / 21 page Video Clock Synthesizer with I2C Programmable Delay MDS ICS1523 Z 10 Revision 052407 Integrated Device Technology, Inc. Tech Support: www.idt.com/go/clockhelp ICS1523 Section 9 Output Termination 9.1 PECL Description The ICS1523 PECL outputs consist of open-drain, current-source, pull-down transistors. An external resistor network permits complete flexibility of logic levels and source impedance. This section describes the design procedure to select the resistor values and the pull-down current for these devices. 9.2 PECL Output Structure The output stage and external circuitry are shown below in Figure 9-1. The output devices are open-drain pull-downs. The two output transistors switch differentially, steering the current source (programmable via RSET) from one output to the other. Figure 9-1 PECL Termination Network For the high logic level, the output transistor is off, so the logic level is set by the ratio of R1 and R2 and the voltage VAA. Generally, VAA will be equal to VDD. For logic low, the pull-down transistor turns on, pulling the output voltage down to the low logic level. Decoupling capacitor C1 should be a 0.01µF high-frequency ceramic unit, and all power pins on the ICS1523 should also be decoupled with similar capacitors. 9.3 PECL Design Assumptions All referenced voltages in this application note are positive and referenced to the GND pin of the chip. However, negative logic levels can be generated by level shifting, i.e. connecting the VDD pin of the device to system ground and the GND pin to a negative voltage. All logic levels must be between GND and the lesser of VAA and VDD. Then, nodal equations are written, with resistances transformed into conductances. RSET ICS1523 RB CLK+ (Pin 21) Destination Device or CLK/2+ (Pin 23) CLK– (Pin 20) or CLK/2– (Pin 22) IREF (Pin 24) VDD IPECL VCC RA RB RA 0.1 µF 0.1 µF IPECL * * * Coaxial cable, microstrip, or stripline, with Z0 = RL. Typically, coaxial cable, microstrip, or stripline is not required if the distance from the ICS1523 to the PECL load is short (that is, < 3 cm). C1 |
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