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ICS1523 Datasheet(PDF) 16 Page - Integrated Device Technology |
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ICS1523 Datasheet(HTML) 16 Page - Integrated Device Technology |
16 / 21 page Video Clock Synthesizer with I2C Programmable Delay ICS1523 MDS ICS1523 Z 16 Revision 052407 Integrated Device Technology, Inc. Tech Support: www.idt.com/go/clockhelp 12.2 Timing for 0x0:2=1 Figure 12-3 0x0:2=1 Timing Diagram Table 12-3 0x0:2=1 Timing Values Symbol Parameter Minimum Typical Maximum Units T2 HSYNC Low to FUNC High Delay T8 + T3 ns T3 HSYNC Low to PECL CLK+ High Delay (DPA Offset = 0) -10 - ns T4 PECL Clock to SSTL_3 Clock Delay 0 0.2 0.6 ns T5 PECL Clock to FUNC Delay 0.6 1.0 1.6 ns T6 PECL Clock to PECL/2 Clock 0.6 1.0 1.6 ns T7 PECL Clock to SSTL_3 CLK/2 Delay 0.4 0.9 1.2 ns T8 PECL Clock High Time - 0.5 - UI |
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