S-7750C

Seiko Instruments Inc.

20

4. Acknowledgment

Data is transmitted sequentially in 8-bit. Changing the SDA line to “L” indicates that the devices on the system bus

have received data, thus the devices send an acknowledgment signal back during the 9th clock of cycle.

The S-7750C does not send an acknowledgment signal back during the Write operation.

1

8

9

Acknowledgment

signal output

Start

Condition

SCL

(

Input)

SDA

(Master device

’s output)

SDA

(

Output)

Figure 23 Acknowledgment Output Timing 1

The both commands, reload command and switching access to register / E

as the command 2-byte or more is possible by adding dummy data. However, the S-7750C executes the command at the

moment that it has loaded 9-bit. And in this case, inputting clock 2-byte or more after inputting these commands makes the

SDA pin set in high-impedance. However, in the acknowledgment timing, S-7750C sends acknowledgment signal back

regardless of the setting at

W

/

R

bit. Figure 24 shows the output timing of acknowledgment signal.

SCL

SDA

High-Impedance

Acknowledgement Signal from S-7750C

R / W

Device Code

Command

(0000 or 0001)

Start Condition

Stop Condition

High-Impedance

Figure 24 Acknowledgment Output Timing 2