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S-1170B18UC-OTDTFG Datasheet(PDF) 10 Page - Seiko Instruments Inc |
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S-1170B18UC-OTDTFG Datasheet(HTML) 10 Page - Seiko Instruments Inc |
10 / 29 page HIGH RIPPLE-REJECTION LOW DROPOUT HIGH OUTPUT CURRENT CMOS VOLTAGE REGULATOR S-1170 Series Rev.3.0_02 Seiko Instruments Inc. 10 Standard Circuit ON/OFF VSS VOUT VIN CIN *1 CL *2 Input Output GND Single GND *1. CIN is a capacitor for stabilizing the input. *2. A ceramic capacitor of 4.7 µF or more can be used for CL. Figure 10 Caution The above connection diagram and constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. Application Conditions Input capacitor (CIN): 4.7 µF or more Output capacitor (CL): 4.7 µF or more ESR of output capacitor: 0.5 Ω or less Caution A general series regulator may oscillate, depending on the external components selected. Check that no oscillation occurs with the application using the above capacitor. Selection of Input and Output Capacitors (CIN, CL) The S-1170 Series requires an output capacitor between the VOUT and VSS pins for phase compensation. A ceramic capacitor with a capacitance of 4.7 µF or more provides a stable operation in all temperature ranges. When using an OS capacitor, tantalum capacitor, or aluminum electrolytic capacitor, a ceramic capacitor with a capacitance of 4.7 µF or more and an ESR of 0.5 Ω or less is required. The output overshoot and undershoot values, which are transient response characteristics, vary depending on the output capacitor value. The required capacitance value for the input capacitor differs depending on the application. The recommended application values are, CIN = 4.7 µF or more and CL = 4.7 µF or more, however, perform a thorough evaluation using the actual device, including evaluation of temperature characteristics. |
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