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S-816A44AMC-BATT2G Datasheet(PDF) 8 Page - Seiko Instruments Inc |
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S-816A44AMC-BATT2G Datasheet(HTML) 8 Page - Seiko Instruments Inc |
8 / 24 page EXTERNAL TRANSISTOR TYPE CMOS VOLTAGE REGULATOR S-816 Series Rev.5.1_00 8 Seiko Instruments Inc. Operation 1. Basic Operation Figure 7 shows a block diagram of the S-816 Series. The device compares the voltage which is obtained from dividing output voltage VOUT by feedback resistances RA and RB with reference voltage VREF through the error amplifier, output of which controls the sink driver. By regulating the base current of the external PNP transistor, the IC maintains a constant output voltage that is not susceptible to an input voltage variation or temperature variation. OUT IN CL EXT VOUT VSS OFF ON/ VIN VREF Current Source Overcurrent Protection Circuit RB RA RC Error Amplifier Sink Driver + − + − Figure 7 2. Internal Circuits 2.1. Shutdown Pin ( OFF ON/ Pin) This pin activates and deactivates the regulating operation. When the shutdown pin is set to "L", the VIN voltage appears through the EXT pin, prodding the external PNP transistor to off. All the internal circuits stop working, and substantial savings in current consumption are achieved accordingly. In this condition, the EXT pin is pulled up to VIN by a pull-up resistance (approx. 0.5 M Ω) inside the IC in order to ensure you power cut off of the external PNP transistor. The shutdown pin is configured as shown in Figure 8. Since neither pull-up or pull-down is performed internally, please avoid using the pin in a floating state. Also, be sure to refrain from applying a voltage of 0.3 V to 2.4 V to this pin lest the current consumption increase. When this shutdown pin is not used, leave it coupled to the VIN pin. Table 5 Shutdown Pin Internal Circuit EXT Pin Voltage VOUT Pin Voltage "H" Activated VIN −VBE Set value "L" Deactivated VIN Hi-Z VIN VSS OFF ON/ Figure 8 |
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