S-93L76A

Seiko Instruments Inc.

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2. Writing (WRITE, ERASE, WRAL, ERAL)

Write instructions (WRITE, ERASE, WRAL, and ERAL) are used to start writing data to the non-volatile

memory by making CS “L” after the specified number of clocks has been input.

used. The typical write time is less than half 10 ms. If the end of the write operation is known,

therefore, the write cycle can be minimized. To ascertain the end of a write operation, make CS “L” to

start the write operation and then make CS “H” again to check the status of the DO output pin. This

series of operations is called a verify operation.

If DO outputs “L” during the verify operation period in which CS is “H”, it indicates that a write operation

is in progress. If DO outputs “H”, it indicates that the write operation is finished. The verify operation

can be executed as many times as required. This operation can be executed in two ways. One is

detecting the positive transition of DO output from “L” to “H” while holding CS at “H”. The other is

detecting the positive transition of DO output from “L” to “H” by making CS “H” once and checking DO

output, and then returning CS to “L”.

During the write period, SK and DI are invalid. Do not input any instructions during this period. Input an

instruction while the DO pin is outputting “H” or is in a high-impedance state. Even while the DO pin is

outputing “H”, DO immediately goes into a high-impedance (Hi-Z) state if “H” of DI (start bit) is input at

the rising edge of SK.

Keep DI “L” during the verify operation period.

2.1 Writing data (WRITE)

This instruction is used to write 16-bit data to a specified address.

After making CS “H”, input a start bit, the WRITE instruction, an address, and 16-bit data. If data of

more than 16 bits is input, the written data is sequentially shifted at each clock, and the 16 bits input

last are the valid data. The write operation is started when CS is made “L”. It is not necessary to

set data to “1” before it is written.

DO

<1>

2

3

4

5

6

7

8

9

10 11

12 13 14

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0

1

X

A8 A7 A6 A5 A4 A3 A2 A1 A0 D15

D0

DI

SK

CS

Hi-Z

Busy

Ready

Standby

Hi-Z

Verify

1

Figure 7 Data Write Timing