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S-25C020A01-T8T1G Datasheet(PDF) 6 Page - Seiko Instruments Inc |
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S-25C020A01-T8T1G Datasheet(HTML) 6 Page - Seiko Instruments Inc |
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6 / 37 page  CMOS SPI SERIAL E2PROM S-25C010A/020A/040A Rev.1.0_00 Seiko Instruments Inc. 6 AC Electrical Characteristics Table 12 Measurement Conditions Input pulse voltage 0.2 × VCC to 0.8 × VCC Output reference voltage 0.5 × VCC Output load 100 pF Table 13 VCC = 1.6 to 2.5 V VCC = 2.5 to 4.5 V VCC = 4.5 to 5.5 V Item Symbol Min. Max. Min. Max. Min. Max. Unit SCK clock frequency fSCK − 2.0 − 5.0 − 5.0 MHz CS setup time during CS falling tCSS.CL 150 − 90 − 90 − ns CS setup time during CS rising tCSS.CH 150 − 90 − 90 − ns CS deselect time tCDS 200 − 90 − 90 − ns CS hold time during CS falling tCSH.CL 200 − 90 − 90 − ns CS hold time during CS rising tCSH.CH 150 − 90 − 90 − ns SCK clock time “H” *1 tHIGH 200 − 90 − 90 − ns SCK clock time “L” *1 tLOW 200 − 90 − 90 − ns Rising time of SCK clock *2 tRSK − 1 − 1 − 1 µs Falling time of SCK clock *2 tFSK − 1 − 1 − 1 µs SI data input setup time tDS 50 − 20 − 20 − ns SI data input hold time tDH 60 − 30 − 30 − ns SCK “L” hold time during HOLD rising tSKH.HH 150 − 70 − 70 − ns SCL “L” hold time during HOLD falling tSKH.HL 100 − 40 − 40 − ns SCK “H” setup time during HOLD falling tSKS.HL 150 − 60 − 60 − ns SCK “H” setup time during HOLD rising tSKS.HH 150 − 60 − 60 − ns Disable time of SO output *2 tOZ − 200 − 100 − 100 ns Delay time of SO output tOD − 150 − 70 − 70 ns Hold time of SO output tOH 0 − 0 − 0 − ns Rising time of SO output *2 tRO − 100 − 40 − 40 ns Falling time of SO output *2 tFO − 100 − 40 − 40 ns Disable time of SO output during HOLD falling *2 tOZ.HL − 200 − 100 − 100 ns Delay time of SO output during HOLD rising *2 tOD.HH − 150 − 50 − 50 ns WP setup time tWS1 0 − 0 − 0 − ns WP hold time tWH1 0 − 0 − 0 − ns WP release / setup time tWS2 0 − 0 − 0 − ns WP release / hold time tWH2 60 − 30 − 30 − ns *1. The clock cycle of the SCK clock (frequency fSCK) is 1/fSCK µs. This clock cycle is determined by a combination of several AC characteristics. Note that the clock cycle cannot be set as (1/fSCK) = tLOW (Min.) + tHIGH (Min.) by minimizing the SCK clock cycle time. *2. These are values of sample and not 100% tested. |
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