P82B96_6

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 06 — 31 January 2008

8 of 28

NXP Semiconductors

P82B96

Dual bidirectional bus buffer

[1]

Limit data for +125

°C applies to P82B96TD/S410 version. It is guaranteed by design/characterization, but not by 100 % test.

[2]

The minimum value requirement for pull-up current, 200

µA, guarantees that the minimum value for V

While the tolerances on absolute levels allow a small probability the LOW from one Sx output is recognized by an Sx input of another

P82B96, this has no consequences for normal applications. In any design the Sx pins of different ICs should never be linked because

[3]

The output logic LOW depends on the sink current. For scaling, see

Application Note AN255.

[4]

The input logic threshold is independent of the supply voltage.

[5]

buffer time delay on

falling input between

output falling 50 %

no capacitive load;

-

250

-

-

-

ns

buffer time delay on

rising input between

output reaching 50 %

no capacitive load;

-

270

-

-

-

ns

Input capacitance

input capacitance

effective input

capacitance of any

signal pin measured

by incremental bus

rise times

--

7

-

7

pF

Table 5.

Symbol

Parameter

Conditions

+125

Unit

Min

Typ

Max

Min

Max