TDA8295 datasheet(9/77 Pages) NXP

Part #	TDA8295

Description	Digital global standard low IF demodulator for analog TV and FM radio

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Manufacturer	NXP [NXP Semiconductors]

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TDA8295_1

Product data sheet

Rev. 01 — 4 February 2008

9 of 77

NXP Semiconductors

TDA8295

Digital global standard low IF demodulator for analog TV and FM radio

[1]

All digital inputs are 5 V tolerant (except pin XIN).

Boundary scan

TMS

24

I

Test mode select provides the logic levels needed to change the TAP controller

from state to state during the boundary scan test.

TRST_N

30

I

Test reset is used to reset the TAP controller (active LOW). Grounding is

mandatory in Functional mode.

TCK

27

I

Test clock is used to drive the TAP controller.

TDI

23

I

Test data input is the serial data input for the test data instruction.

TDO

22

O

Test data output is the serial test data output pin. The data is provided on the

falling edge of TCK.

ADC

IF_POS

1

AI

IF positive analog input for internal ADC

IF_NEG

2

AI

IF negative analog input for internal ADC

DAC

V_IOUTP

14

AO

positive analog current output of the video output

V_IOUTN

13

AO

negative analog current output of the video output

S_IOUTP

17

AO

positive analog current output of the SSIF/mono sound output

S_IOUTN

16

AO

negative analog current output of the SSIF/mono sound output

RSET

11

I

External bias setting of the DACs. An external resistor (1 k

Ω typical) has to be

connected between RSET and the analog ground of the board. This resistor

generates the current into the DACs and also deﬁnes the full scale output

current. The total parasitic capacitance seen externally from the RSET pin has to

be lower than 20 pF.

Supplies and grounds

VDDA(DAC1)(3V3)

15

PS

DAC1 (video DAC) and DAC reference module analog supply voltage (3.3 V

typical)

VDDA(DAC2)(3V3)

18

PS

DAC2 (sound DAC) analog supply voltage (3.3 V typical)

VSSA(DAC)

12

GND

DAC reference module analog ground supply voltage (0 V typical)

VDDA(ADC)(3V3)

3

PS

IF ADC analog supply voltage (3.3 V typical)

VDDD(ADC)(3V3)

39

PS

IF ADC digital supply voltage (3.3 V typical)

VSSA(ADC)

40

GND

ADC analog ground supply voltage (0 V typical)

VDDD1(1V2)

4

PS

ADC, PLL and DACs digital supply voltage (1.2 V typical)

VSSD1

5

GND

ADC, PLL and DACs digital ground supply voltage (0 V typical)

VDDA(PLL)(1V2)

7

PS

crystal oscillator and clock PLL analog supply voltage (1.2 V typical)

VSSA(PLL)

10

GND

crystal oscillator and clock PLL analog ground supply voltage (0 V typical)

VDDD2(1V2)

25

PS

core digital supply voltage (1.2 V typical)

VSSD2

26

GND

core digital ground supply voltage (0 V typical)

VDDDR(3V3)

34

PS

ring digital supply voltage (3.3 V typical)

VSSDR

35

GND

ring digital ground supply voltage (0 V typical)

Other pins

i.c.

36

I

internally connected; connect to ground

i.c.

38

I

internally connected; connect to ground

i.c.

6

I

internally connected; connect to ground

Table 4.

Pin description …continued

Symbol

Type[1][2]

Description

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