SC16C850V datasheet(47/47 Pages) NXP

Part #	SC16C850V

Description	1.8 V single UART, 5 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA), and XScale VLIO bus interface

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Manufacturer	NXP [NXP Semiconductors]

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NXP Semiconductors

SC16C850V

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 14 January 2008

Document identifier: SC16C850V_4

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

17. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3

Ordering information . . . . . . . . . . . . . . . . . . . . . 2

4

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5

Pinning information . . . . . . . . . . . . . . . . . . . . . . 4

5.1

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5.2

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

6

Functional description . . . . . . . . . . . . . . . . . . . 6

6.1

UART selection . . . . . . . . . . . . . . . . . . . . . . . . . 6

6.2

Extended mode (128-byte FIFO) . . . . . . . . . . . 7

6.3

Internal registers . . . . . . . . . . . . . . . . . . . . . . . . 7

6.4

FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . . 8

6.4.1

32-byte FIFO mode. . . . . . . . . . . . . . . . . . . . . . 8

6.4.2

128-byte FIFO mode. . . . . . . . . . . . . . . . . . . . . 8

6.5

Hardware ﬂow control . . . . . . . . . . . . . . . . . . . . 8

6.6

Software ﬂow control . . . . . . . . . . . . . . . . . . . . 9

6.7

Special character detect . . . . . . . . . . . . . . . . . 10

6.8

Interrupt priority and time-out interrupts . . . . . 10

6.9

Programmable baud rate generator . . . . . . . . 11

6.10

Loopback mode . . . . . . . . . . . . . . . . . . . . . . . 13

6.11

Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.11.1

Conditions to enter Sleep mode . . . . . . . . . . . 15

6.11.2

Conditions to resume normal operation . . . . . 15

6.12

Low power feature . . . . . . . . . . . . . . . . . . . . . 15

6.13

RS-485 Features . . . . . . . . . . . . . . . . . . . . . . 16

6.13.1

Auto RS-485 RTS control . . . . . . . . . . . . . . . . 16

6.13.2

RS-485 RTS inversion . . . . . . . . . . . . . . . . . . 16

6.13.3

Auto 9-bit mode (RS-485) . . . . . . . . . . . . . . . . 16

6.13.3.1

Normal Multi-drop mode . . . . . . . . . . . . . . . . . 16

6.13.3.2

Auto address detection . . . . . . . . . . . . . . . . . . 17

7

Register descriptions . . . . . . . . . . . . . . . . . . . 17

7.1

Transmit (THR) and Receive (RHR) Holding

Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.2

Interrupt Enable Register (IER) . . . . . . . . . . . 20

7.2.1

IER versus transmit/receive FIFO interrupt

mode operation. . . . . . . . . . . . . . . . . . . . . . . . 21

7.2.2

IER versus receive/transmit FIFO polled

mode operation. . . . . . . . . . . . . . . . . . . . . . . . 21

7.3

FIFO Control Register (FCR) . . . . . . . . . . . . . 22

7.3.1

FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.4

Interrupt Status Register (ISR) . . . . . . . . . . . . 23

7.5

Line Control Register (LCR) . . . . . . . . . . . . . . 24

7.6

Modem Control Register (MCR) . . . . . . . . . . . 25

7.7

Line Status Register (LSR) . . . . . . . . . . . . . . . 26

7.8

Modem Status Register (MSR). . . . . . . . . . . . 27

7.9

Extra Feature Control Register (EFCR) . . . . . 28

7.10

Scratchpad Register (SPR) . . . . . . . . . . . . . . 28

7.11

Division Latch (DLL and DLM) . . . . . . . . . . . . 28

7.12

Transmit FIFO Level Count (TXLVLCNT) . . . . 28

7.13

Receive FIFO Level Count (RXLVLCNT) . . . . 28

7.14

Enhanced Feature Register (EFR). . . . . . . . . 29

7.15

Transmit Interrupt Level register (TXINTLVL) . 30

7.16

Receive Interrupt Level register (RXINTLVL) . 30

7.17

Flow Control Trigger Level High (FLWCNTH). 31

7.18

Flow Control Trigger Level Low (FLWCNTL) . 31

7.19

Clock prescaler (CLKPRES) . . . . . . . . . . . . . 31

7.20

RS-485 turn-around time delay (RS485TIME) 32

7.21

Advanced Feature Control Register 1

(AFCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.22

Advanced Feature Control Register 2

(AFCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.23

SC16C850V external reset condition and

software reset. . . . . . . . . . . . . . . . . . . . . . . . . 34

8

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 35

9

Static characteristics . . . . . . . . . . . . . . . . . . . 35

10

Dynamic characteristics . . . . . . . . . . . . . . . . . 36

10.1

Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . 37

11

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 41

12

Soldering of SMD packages . . . . . . . . . . . . . . 42

12.1

Introduction to soldering. . . . . . . . . . . . . . . . . 42

12.2

Wave and reﬂow soldering . . . . . . . . . . . . . . . 42

12.3

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 42

12.4

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 43

13

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 44

14

Revision history . . . . . . . . . . . . . . . . . . . . . . . 45

15

Legal information . . . . . . . . . . . . . . . . . . . . . . 46

15.1

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 46

15.2

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

15.3

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 46

15.4

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 46

16

Contact information . . . . . . . . . . . . . . . . . . . . 46

17

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

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